PRELIMINARY W942508AH
8M
×
4 BANKS
×
8 BIT DDR SDRAM
GENERAL DESCRIPTION
W942508AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 8,388,608 words
×
4 banks
×
8 bits. Using pipelined architecture and 0.175
µm
process technology, W942508AH delivers a data bandwidth of up to 256M words per second (-6). To
fully comply with the personal computer industrial standard, W942508AH is sorted into four speed
grades: -6 ,-7, -75 The -6 is compliant to the 166 MHz/CL2.5 or DDR333/CL2.5 specification,
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942508AH is ideal for main memory in
high performance applications.
FEATURES
•
2.5V
±
0.1V Power Supply
•
Up to 166 MHz Clock Frequency
•
Double Data Rate architecture; two data transfers per clock cycle
•
•
•
•
•
•
•
•
•
•
•
Differential clock inputs (CLK and CLK )
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2 and 2.5
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
8K Refresh cycles / 64 mS
Interface: SSTL-2
Packaged in TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
-6
t
CK
t
RAS
t
RC
I
DD1
I
DD4
I
DD6
CL=2
CL=2.5
Active to Precharge Command Period
Active to Ref/Active Command Period
Operation Current (Single bank)
Burst Operation Current
Self-Refresh Current
Clock Cycle Time
min.
min.
min.
min.
max.
max.
max.
7.5 nS
6 nS
42 nS
60 nS
110mA
165mA
3mA
-1-
Publication Release Date: July 2001
Revision 0.91
W942508AH
PIN CONFIGURATION
V
DD
DQ0
V
DD
Q
NC2
DQ1
V
SS
Q
NC2
DQ2
V
DD
Q
NC2
DQ3
V
SS
Q
NC2
NC1
V
DD
Q
NC2
NC1
V
DD
NC1
NC2
WE
CAS
RAS
CS
NC1
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ7
V
SS
Q
NC2
DQ6
V
DD
Q
NC2
DQ5
V
SS
Q
NC2
DQ4
V
DD
Q
NC2
NC1
V
SS
Q
DQS
NC1
V
REF
V
SS
DM
CLK
CLK
CKE
NC1
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
-2-
W942508AH
PIN DESCRIPTION
Pin Number
28−32,35−42
Pin
Name
Function
Address
Description
Multiplexed pins for row and column address.
Row address: A0
−
A12.
Column address: A0
−
A9. (A10 is used for Auto Precharge)
Select bank to activate during row address latch time, or bank to
read/write during column address latch time.
The DQ0 – DQ7 input and output data are synchronized with both
edges of DQS.
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
A0
−
A12
26,27
BS0, BS1
Bank Select
Data Input/
Output
Data Strobe
2,5,8,11,56,59,
DQ0
−
DQ7
62,65
51
DQS
24
CS
Chip Select
23,22,21
47
45,46
RAS , CAS ,
WE
Command Inputs Command inputs (along with
CS
) define the command being
entered.
Write mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
DM
CLK,
CLK
Differential clock All address and control input signals are sampled on the crossing
inputs
of the positive edge of CLK and negative edge of
CLK
.
Clock Enable
Reference
Voltage
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode, or Self Refresh mode is
entered.
V
REF
is reference voltage for inputs.
44
49
1,18,33
34,48,66
3,9,15,55,61
6,12,52,58,64
CKE
V
REF
V
DD
V
SS
V
DD
Q
V
SS
Q
Power ( +2.5V ) Power for logic circuit inside DDR SDRAM.
Ground
Ground for logic circuit inside DDR SDRAM.
Power ( + 2.5V ) Separated power from V
DD
, used for output buffer, to improve
for I/O buffer noise.
Ground for I/O
buffer
Separated ground from V
SS
, used for output buffer, to improve
noise.
4,7,10,13,14,16
,17,19,20,25,43
NC1, NC2
,50,53,54,57,60
,63
No Connection No connection
-3-
Publication Release Date: July 2001
Revision 0.91
W942508AH
BLOCK DIAGRAM
CLK
CLK
DLL
CLOCK
BUFFER
CKE
CONTROL
CS
SIGNAL
RAS
CAS
GENERATOR
COMMAND
DECODER
WE
ROW DECODER
COLUMN DECODER
COLUMN DECODER
ROW DECODER
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A0
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9
A11
A12
BA1
BA0
PREFETCH REGISTER
DQ
DATA CONTROL
CIRCUIT
REFRESH
COUNTER
COLUMN
COUNTER
BUFFER
DQ0
DQ7
DQS
DM
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 8912 * 1024 * 8
-4-
W942508AH
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
IN
, V
OUT
V
DD
, V
DD
Q
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
PARAMETER
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
RATING
-0.3 ~ V
DD
Q +0.3
-0.3 ~ 3.6
0 ~ 70
-55 ~ 150
260
1
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C)
SYMBOL
V
DD
V
DD
Q
V
REF
V
TT
V
IH (DC)
V
IL (DC)
V
ICK (DC
)
V
ID (DC)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input reference Voltage
Termination Voltage (System)
Input High Voltage (DC)
Input Low Voltage (DC)
Differential Clock DC Input Voltage
Input Differential Voltage. CLK and
CLK inputs (DC)
V
IH (AC)
V
IL (AC)
V
ID (AC)
Input High Voltage (AC)
Input Low Voltage (AC)
Input Differential Voltage. CLK and
CLK inputs (AC)
V
X (AC)
V
ISO (AC)
Differential AC input Cross Point
Voltage
Differential Clock AC Middle Point
V
DD
Q/2 - 0.2
V
DD
Q/2 - 0.2
-
-
V
DD
Q/2 + 0.2
V
DD
Q/2 + 0.2
V
V
12, 15
14, 15
V
REF
+ 0.31
-
0.7
-
-
-
-
V
REF
- 0.31
V
DD
Q + 0.6
V
V
V
2
2
13,15
MIN.
2.4
2.4
0.49 x V
DD
Q
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
TYP.
2.5
2.5
0.50 x V
DD
Q
V
REF
-
-
-
-
MAX.
2.6
VDD
0.51 x V
DD
Q
V
REF
+ 0.04
V
DD
Q + 0.3
V
REF
- 0.15
V
DD
Q + 0.3
V
DD
Q + 0.6
UNIT
V
V
V
V
V
V
V
V
NOTES
2
2
2,3
2,8
2
2
15
13,15
Note : Undershoot Limit : V
IL
(min) = -0.9V with a pulse width < 5 nS
Overshoot Limit : V
IH
(max) = V
DD
Q+0.9V with a pulse width < 5 nS
V
IH(DC)
and V
IL(DC)
are levels to maintain the current logic state.
V
IH(AC)
and V
IL(AC)
are levels to change to the new logic state.
-5-
Publication Release Date: July 2001
Revision 0.91
