PRELIMINARY W942516AH
4M
×
4 BANKS
×
16 BIT DDR SDRAM
GENERAL DESCRIPTION
W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words
×
4 banks
×
16 bits. Using pipelined architecture and 0.175
µm
process technology, W942516AH delivers a data bandwidth of up to 286M words per second (-7).
To fully comply with the personal computer industrial standard, W942516AH is sorted into three speed
grades: -7, -75 and -8. The -7 is compliant to the 143 MHz/CL2.5 or DDR266/CL2 specification, the -
75 is compliant to the DDR266/CL2.5 specification, the -8 is compliant to the DDR200/CL2
specification
All Inputs reference to the positive edge of CLK (except for DQ, DM, and CKE). The timing reference
point for the differential clock is when the CLK and CLK signals cross during a transition. And Write
and Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W942516AH is ideal for main memory in
high performance applications.
FEATURES
•
2.5V
±
0.2V Power Supply
•
Up to 143 MHz Clock Frequency
•
Double Data Rate architecture; two data transfers per clock cycle
•
Differential clock inputs (CLK and CLK )
•
DQS is edge-aligned with data for Read; center-aligned with data for Write
•
CAS Latency: 2 and 2.5
•
Burst Length: 2, 4, and 8
•
Auto Refresh and Self Refresh
•
Precharged Power Down and Active Power-Down
•
Write Data Mask
•
Write Latency = 1
•
8K Refresh cycles / 64 mS
•
Interface: SSTL-2
•
Packaged: TSOP II 66 pin, 400 x 875mil , 0.65mm pin pitch
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
-7
-75
-8
t
CK
t
RAS
t
RC
I
DD1
I
DD4
I
DD6
CL=2
CL=2.5
Active to Precharge Command Period
Active to Ref/Active Command Period
Operation Current (Single bank)
Burst Operation Current
Self-Refresh Current
Clock Cycle Time
min.
min.
min.
min.
max.
max.
max.
7.5 nS
7 nS
45 nS
65 nS
110mA
165mA
3mA
8 nS
7.5 nS
45 nS
65 nS
110mA
155mA
3mA
10 nS
8 nS
50 nS
70 nS
100mA
150mA
3mA
-1-
Publication Release Date: May 2001
Revision .0.0
W942516AH
PIN CONFIGURATION (TOP VIEW)
V
DD
DQ0
V
DD
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
DD
Q
DQ5
DQ6
V
SS
Q
DQ7
NC
V
DD
Q
LDQS
NC
V
DD
NC
LDM
WE
CAS
RAS
CS
NC
BS0
BS1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
NC
V
REF
V
SS
UDM
CLK
CLK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
-2-
W942516AH
PIN DESCRIPTION
Pin Number
28−32,35−42
Pin
Name
Function
Address
Description
Multiplexed pins for row and column address.
Row address : A0
−
A12.
Column address: A0
−
A8. (A10 is used for Auto Precharge)
Select bank to activate during row address latch time, or bank to
read/write during column address latch time.
The DQ0 – DQ15 input and output data are synchronized with
both edges of DQS.
DQS is Bi-directional signal. DQS is input signal during write
operation and output signal during read operation. It is Edge-
aligned with read data, Center-aligned with write data.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
A0
−
A12
26,27
2,4,5,7,8,10,11,
13,54,56,57,59,
60,62,63,65
51
BS0, BS1
DQ0
−
DQ15
DQS
Bank Select
Data Input/
Output
Data Strobe
24
CS
Chip Select
23,22,21
47
45,46
RAS , CAS ,
WE
Command Inputs Command inputs (along with
CS
) define the command being
entered.
Write mask
When DM is asserted “high” in burst write, the input data is
masked. DM is synchronized with both edges of DQS.
DM
CLK,
CLK
CKE
V
REF
V
DD
V
SS
V
DD
Q
V
SS
Q
NC
Differential clock Clock inputs, all inputs reference to the positive edge of CLK
inputs
(except for DQ, DM and CKE).
Clock Enable
Reference
Voltage
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode, or Self Refresh mode is
entered.
V
REF
is reference voltage for inputs buffers.
44
49
1,18,33
34,48,66
3,9,15,55,61
6,12,52,58,64
14,17,19,25,43,
50,53
Power ( +2.5V ) Power for logic circuit inside DDR SDRAM.
Ground
Ground for logic circuit inside DDR SDRAM.
Power ( + 2.5V ) Separated power from V
DD
, used for output buffer, to improve
for I/O buffer noise.
Ground for I/O
buffer
Separated ground from V
SS
, used for output buffer, to improve
noise.
No Connection No connection
-3-
Publication Release Date: May 2001
Revision 0.0
W942516AH
BLOCK DIAGRAM
CLK
CLK
DLL
CLOCK
BUFFER
CKE
CONTROL
CS
RAS
CAS
DECODER
SIGNAL
GENERATOR
COMMAND
WE
COLUMN DECODER
COLUMN DECODER
ROW DECODER
A10
CELL ARRAY
BANK #0
ROW DECODER
CELL ARRAY
BANK #1
A0
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
A9
A11
A12
BA1
BA0
PREFETCH REGISTER
DQ
DATA CONTROL
CIRCUIT
REFRESH
COUNTER
COLUMN
COUNTER
BUFFER
DQ0
DQ15
LDQS, UDQS
LDM, UDM
COLUMN DECODER
COLUMN DECODER
ROW DECODER
CELL ARRAY
BANK #2
ROW DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 8912 * 512 * 16
-4-
W942516AH
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
SYMBOL
V
IN
, V
OUT
V
DD
, V
DD
Q
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
RATING
-0.3 ~ V
DD
Q +0.3
-0.3 ~ 3.6
0 ~ 70
-55 ~ 150
260
1
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input reference Voltage
Termination Voltage (System)
Input High Voltage (DC)
Input Low Voltage (DC)
Differential Clock DC Input Voltage
Input Differential Voltage. CLK and
CLK inputs (DC)
Input High Voltage (AC)
Input Low Voltage (AC)
Input Differential Voltage. CLK and
CLK inputs (AC)
Differential AC input Cross Point
Voltage
Differential Clock AC Middle Point
VX
(AC)
V
ISO (AC)
V
DD
Q/2 - 0.2
V
DD
Q/2 - 0.2
-
-
V
DD
Q/2 + 0.2
V
DD
Q/2 + 0.2
V
V
12, 15
14, 15
V
IH (AC)
V
IL (AC)
V
ID (AC)
V
REF
+ 0.31
-
0.7
-
-
-
-
V
REF
- 0.31
V
DD
Q + 0.6
V
V
V
2
2
13,15
SYMBOL
V
DD
V
DD
Q
V
REF
V
TT
V
IH (DC)
V
IL (DC)
V
ICK (DC
)
V
ID (DC)
MIN.
2.3
2.3
0.49 x V
DD
Q
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
TYP.
2.5
2.5
0.50 x V
DD
Q
V
REF
-
-
-
-
MAX.
2.7
VDD
0.51 x V
DD
Q
V
REF
+ 0.04
V
DD
Q + 0.3
V
REF
- 0.15
V
DD
Q + 0.3
V
DD
Q + 0.6
UNIT
V
V
V
V
V
V
V
V
NOTES
2
2
2,3
2,8
2
2
15
13,15
Note : Undershoot Limit : V
IL
(min) = -0.9V with a pulse width < 5 nS
Overshoot Limit : V
IH
(max) = V
DD
Q+0.9V with a pulse width < 5 nS
V
IH(DC)
and V
IL(DC)
are levels to maintain the current logic state.
V
IH(AC)
and V
IL(AC)
are levels to change to the new logic state.
-5-
Publication Release Date: May 2001
Revision 0.0
