W9425G6DH
4M
×
4 BANKS
×
16 BITS DDR SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION............................................................................................................. 4
FEATURES .................................................................................................................................... 4
KEY PARAMETERS ...................................................................................................................... 5
PIN CONFIGURATION .................................................................................................................. 6
PIN DESCRIPTION........................................................................................................................ 7
BLOCK DIAGRAM ......................................................................................................................... 8
FUNCTIONAL DESCRIPTION....................................................................................................... 9
7.1
7.2
Power Up Sequence............................................................................................................ 9
Command Function ............................................................................................................. 9
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
Bank Activate Command ........................................................................................................9
Bank Precharge Command ....................................................................................................9
Precharge All Command ........................................................................................................9
Write Command .....................................................................................................................9
Write with Auto-precharge Command...................................................................................10
Read Command ...................................................................................................................10
Read with Auto-precharge Command ..................................................................................10
Mode Register Set Command ..............................................................................................10
Extended Mode Register Set Command ..............................................................................10
7.2.10 No-Operation Command ......................................................................................................10
7.2.11 Burst Read Stop Command..................................................................................................11
7.2.12 Device Deselect Command ..................................................................................................11
7.2.13 Auto Refresh Command .......................................................................................................11
7.2.14 Self Refresh Entry Command...............................................................................................11
7.2.15 Self Refresh Exit Command .................................................................................................11
7.2.16 Data Write Enable /Disable Command .................................................................................12
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Read Operation ................................................................................................................. 12
Write Operation ................................................................................................................. 12
Precharge .......................................................................................................................... 13
Burst Termination .............................................................................................................. 13
Refresh Operation ............................................................................................................. 13
Power Down Mode ............................................................................................................ 13
Input Clock Frequency Change during Precharge Power Down Mode ............................ 14
Mode Register Operation .................................................................................................. 14
7.10.1 Burst Length field (A2 to A0) ................................................................................................14
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Publication Release Date:Feb. 12, 2008
Revision A8
W9425G6DH
7.10.2 Addressing Mode Select (A3)...............................................................................................14
7.10.3 CAS Latency field (A6 to A4)................................................................................................16
7.10.4 DLL Reset bit (A8) ................................................................................................................16
7.10.5 Mode Register /Extended Mode register change bits (BS0, BS1) ........................................16
7.10.6 Extended Mode Register field ..............................................................................................16
7.10.7 Reserved field ......................................................................................................................16
8.
OPERATION MODE .................................................................................................................... 17
8.1
8.2
8.3
8.4
Simplified Truth Table........................................................................................................ 17
Function Truth Table ......................................................................................................... 18
Function Truth Table for CKE............................................................................................ 21
Simplified Stated Diagram ................................................................................................. 22
Absolute Maximum Ratings............................................................................................... 23
Recommended DC Operating Conditions ......................................................................... 23
Capacitance....................................................................................................................... 24
Leakage and Output Buffer Characteristics ...................................................................... 24
DC Characteristics............................................................................................................. 25
AC Characteristics and Operating Condition..................................................................... 26
AC Test Conditions............................................................................................................ 28
Table 1: Input Slew Rate for DQ, DQS, and DM ............................................................... 30
Table 2: Input Setup & Hold Time Derating for Slew Rate................................................ 30
Table 3: Input/Output Setup & Hold Time Derating for Slew Rate .................................... 30
Table 4: Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate .................... 30
Table 5: Output Slew Rate Characteristics (X16 Devices only) ........................................ 30
Table 6: Output Slew Rate Matching Ratio Characteristics .............................................. 31
Table 7: AC Overshoot/Undershoot Specification for Address and Control Pins ............. 31
Table 8: Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins .............. 32
System Notes: ................................................................................................................... 33
Command Input Timing ..................................................................................................... 35
Timing of the CLK Signals ................................................................................................. 35
Read Timing (Burst Length = 4) ........................................................................................ 36
Write Timing (Burst Length = 4) ........................................................................................ 37
DM, DATA MASK (W9425G6DH) ..................................................................................... 38
Mode Register Set (MRS) Timing ..................................................................................... 39
Extend Mode Register Set (EMRS) Timing....................................................................... 40
Publication Release Date:Feb. 12, 2008
Revision A8
9.
ELECTRICAL CHARACTERISTICS ............................................................................................ 23
9.1
9.2
9.3
9.4
9.5
9.6
9.7
10.
SYSTEM CHARACTERISTICS FOR DDR SDRAM .................................................................... 30
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11.
TIMING WAVEFORMS ................................................................................................................ 35
11.1
11.2
11.3
11.4
11.5
11.6
11.7
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W9425G6DH
11.8
11.9
Auto-precharge Timing (Read Cycle, CL = 2) ................................................................... 41
Auto-precharge Timing (Read cycle, CL = 2), continued .................................................. 42
11.10 Auto-precharge Timing (Write Cycle) ................................................................................ 43
11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8) .............................................................. 44
11.12 Burst Read Stop (BL = 8) .................................................................................................. 44
11.13 Read Interrupted by Write & BST (BL = 8)........................................................................ 45
11.14 Read Interrupted by Precharge (BL = 8) ........................................................................... 45
11.15 Write Interrupted by Write (BL = 2, 4, 8) ........................................................................... 46
11.16 Write Interrupted by Read (CL = 2, BL = 8)....................................................................... 46
11.17 Write Interrupted by Read (CL = 3, BL = 4)....................................................................... 47
11.18 Write Interrupted by Precharge (BL = 8) ........................................................................... 47
11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 48
11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 48
11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2) ......................................................... 49
11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4) ......................................................... 49
11.23 Auto Refresh Cycle............................................................................................................ 50
11.24 Precharge/Activate Power Down Mode Entry and Exit Timing ......................................... 50
11.25 Input Clock Frequency Change during Precharge Power Down Mode Timing................. 50
11.26 Self Refresh Entry and Exit Timing ................................................................................... 51
12.
13.
PACKAGE SPECIFICATION ....................................................................................................... 52
12.1
TSOP 66 lI – 400 mil ......................................................................................................... 52
REVISION HISTORY ................................................................................................................... 53
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Publication Release Date:Feb. 12, 2008
Revision A8
W9425G6DH
1. GENERAL DESCRIPTION
W9425G6DH is a CMOS Double Data Rate synchronous dynamic random access memory (DDR
SDRAM), organized as 4,194,304 words
×
4 banks
×
16 bits. Using pipelined architecture and 0.11 µm
process technology, W9425G6DH delivers a data bandwidth of up to 500M words per second (-4). To
fully comply with the personal computer industrial standard, W9425G6DH is sorted into the following
speed grades: -4/-5/-6/-6F/-6I/-75 and 75I. The -4 is compliant to the DDR500/CL3 specification. The -
5 is compliant to the DDR400/CL3 specification. The -6/-6F is compliant to the DDR333/CL2.5
specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the
DDR266/CL2 specification (the 75I grade which is guaranteed to support -40°C ~ 85°C).
All Input reference to the positive edge of CLK (except for DQ, DM and CKE). The timing reference
point for the differential clock is when the CLK and
CLK
signals cross during a transition. Write and
Read data are synschronized with the both edges of DQS (Data Strobe).
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9425G6DH is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.5V
±0.2V
Power Supply for DDR266/DDR333
2.6V
±0.1V
Power Supply for DDR400/DDR500
Up to 250 MHz Clock Frequency
Double Data Rate architecture; two data transfers per clock cycle
Differential clock inputs (CLK and
CLK
)
DQS is edge-aligned with data for Read; center-aligned with data for Write
CAS Latency: 2, 2.5 and 3
Burst Length: 2, 4 and 8
Auto Refresh and Self Refresh
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = 1
7.8µS refresh interval (8K / 64 mS refresh)
Maximum burst refresh cycle: 8
Interface: SSTL_2
Packaged in TSOP II 66-pin, 400 mil, 0.65 mm pin pitch, using Pb free with RoHS compliant
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Publication Release Date:Feb. 12, 2008
Revision A8
W9425G6DH
3. KEY PARAMETERS
SYMBOL
DESCRIPTION
CL = 2
MIN./MAX.
Min.
Max.
t
CK
-4
-
-
-
-
4 nS
10 nS
36 nS
52 nS
110 mA
-5
7.5 nS
10 nS
6 nS
10 nS
5 nS
10 nS
40 nS
55 nS
110 mA
-6/-6F/-6I
7.5 nS
12 nS
6 nS
12 nS
6 nS
12 nS
42 nS
60 nS
110 mA
-75/75I
7.5 nS
12 nS
7.5 nS
12 nS
7.5 nS
12 nS
45 nS
67.5 nS
110 mA
Clock Cycle Time
CL = 2.5
Min.
Max.
CL = 3
t
RAS
t
RC
I
DD0
Active to Precharge Command
Period
Active to Ref/Active Command
Period
Operating Current:
One Bank Active-Precharge
Operating Current:
One Bank Active-Read-Precharge
Burst Operation Read Current
Burst Operation Write Current
Auto Refresh Current
Self Refresh Current
Min.
Max.
Min.
Min.
Max.
I
DD1
I
DD4R
I
DD4W
I
DD5
I
DD6
Max.
Max.
Max.
Max.
Max.
150 mA
190 mA
190 mA
190 mA
5 mA
150 mA
180 mA
180 mA
190 mA
3 mA
150 mA
170 mA
170 mA
190 mA
3 mA
150 mA
160 mA
160 mA
190 mA
3 mA
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Publication Release Date:Feb. 12, 2008
Revision A8
PCB设计
