W9451GBDA
512MB (64M
×
64) DDR SDRAM DIMM
1. GENERAL DESCRIPTION
The W9451GBDA is a 512MB Double Data Rate Synchronous Dynamic RAM (DDR SDRAM) memory
modules. It is organized in a 64M x 64 bit configuration using eight pieces of Winbond W942508BH
(64M x 8 bits) DDR SDRAMs and assembled on a JEDEC standard 184-pin DIMM PCB.
To provide high data bandwidth, W9451GBDA uses a double data rate architecture to transfer two
data words per clock cycle and delivers a data bandwidth of up to 2.1G (DDR266) bytes per second. It
is ideal for high performance systems that require fast data transfer memory modules.
By reading the Serial Presence-Detect (SPD), the system can identify the module type, DDR SDRAM
timing parameters and other necessary information to optimize system setting and maximize its
performance.
2. FEATURES
•
JEDEC standard 184-pin, Dual In-Line Memory Module (DIMM)
•
Comply to DDR266 and DDR200 specification
•
Two memory rows on this module
•
Differential clock inputs (CLK and CLK )
•
Double Data Rate architecture, two data transfers per clock cycle
•
CAS Latency: 2 and 2.5
•
Burst Lengths: 2, 4, 8
•
Auto Refresh and Self Refresh
•
8K refresh cycles / 64 ms
•
Serial Presence Detect with EEPROM
•
Interface: SSTL-2
•
Power supply: 2.5V
±0.2V
•
PCB height: 1.25 inches
3. AVAILABLE PART NUMBERS
MODULE PART NUMBER
W9451GBDA-7
W9451GBDA-75
SPEED
DDR266/CL2
DDR266/CL2.5
-1-
Publication Release Date: March 15, 2002
Revision A1
W9451GBDA
4. PIN ASSIGNMENT
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FONT
V
REF
DQ0
V
SS
DQ1
DQS0
DQ2
V
DD
DQ3
NC
NC
V
SS
DQ8
DQ9
DQS1
V
DDQ
CKL1
CLK1
PIN
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
FONT
A5
DQ24
V
SS
DQ25
DQS3
A4
V
DD
DQ26
DQ27
A2
V
SS
A1
*CB0
*CB1
V
DD
*DQS8
A0
*CB2
V
SS
*CB3
BA1
KEY
PIN
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
FONT
V
DDQ
WE
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
BACK
V
SS
DQ4
DQ5
V
DD
Q
DQS9
DQ6
DQ7
V
SS
NC
NC
*A13
V
DDQ
DQ12
DQ13
DQS10
V
DD
DQ14
DQ15
CKE1
V
DDQ
*BA2
DQ20
A12
V
SS
DQ21
A11
DQS11
V
DD
DQ22
A8
DQ23
PIN
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
BACK
V
SS
A6
DQ28
DQ29
V
DDQ
DQS12
A3
DQ30
V
SS
DQ31
*CB4
*CB5
V
DDQ
CLK0
CLK
0
PIN
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
17
177
178
179
180
181
182
183
184
BACK
RAS
DQ45
V
DDQ
CS0
CS1
DQ41
CAS
V
SS
DQS5
DQ42
DQ43
V
DD
*S2
DQ48
DQ49
VSS
CLK2
DQS14
V
SS
DQ46
DQ47
*S3
V
DDQ
DQ52
DQ53
NC
V
DD
DQS15
DQ54
DQ55
V
DDQ
NC
DQ60
DQ61
V
SS
DQS16
DQ62
DQ63
V
DDQ
SA0
SA1
SA2
V
DDSPD
CLK2
V
DDQ
DQS6
DQ50
DQ51
V
SS
V
DDID
DQ56
DQ57
V
DD
DQS7
DQ58
DQ59
V
SS
WP
SDA
SCL
V
SS
*DQS17
A10
*CB6
V
DDQ
*CB7
KEY
V
SS
DQ10
DQ11
CKE0
V
DDQ
DQ16
DQ17
DQS2
V
SS
A9
DQ18
A7
V
DD
Q
DQ19
53
54
55
56
57
58
59
60
61
DQ32
V
DDQ
DQ33
DQS4
DQ34
V
SS
BA0
DQ35
DQ40
145
146
147
148
149
150
151
152
153
V
SS
DQ36
DQ37
V
DD
DQS13
DQ38
DQ39
V
SS
DQ44
*These pins are not used in this module.
-2-
W9451GBDA
5. PIN DESCRIPTIONS
PIN
CLKn,
CLKn
Clock Input
NAME
FUNCTION DESCRIPTION
CLKn and
CLKn
are differential clock inputs. All input
command signals are sampled at the positive edge of
CLK(except for DQ, DM and CKE).
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
CKE controls the clock activation and deactivation. When CKE
is low, Power Down mode, Suspend mode, or Self-Refresh
mode is entered.
Multiplexed pins for row and column address.
Row address: A0
−
A12. Column address: A0
−
A9.
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Command input. When sampled at the rising edge of the
clock,
RAS
,
CAS
and
WE
define the operation to be
executed.
Referred to
RAS
Referred to
RAS
The output buffer is placed at Hi-Z when DM is sampled high
in read cycle. In write cycle, sampling DM high will block the
write data.
Multiplexed pins for data output and input
Output with read data, input with write data. DQS is edge-
aligned with read data, centered in write data.
Power supply (2.5V).
Ground
SSTL-2 Reference voltage
Separated power supply for SPD EEPROM (2.3V
−
3.6V)
Clock for serial presence detection
Data line for serial presence detection
System assigned address (SA0
−
SA2) to identify different
memory module in a system board.
No connection
CSn
Chip Select
CKEn
A0
−
A12
BA0
−
BA1
Clock Enable
Address
Bank Select
Address
Row Address
Strobe
Column Address
Strobe
Write Enable
Input/Output Mask
Data Input/Output
Data Strobe
Input/Output
Power (+2.5V)
Ground
Reference Voltage
SPD Power
Serial Clock
Serial Data I/O
SPD Address Line
No Connection
RAS
CAS
WE
DM0
−
DM7
DQ0
−
DQ63
DQS0
−
DQS7
V
DD
V
SS
V
REF
V
DDSPD
SCL
SDA
SAn
NC
-3-
Publication Release Date: March 15, 2002
Revision A1
W9451GBDA
6. BLOCK DIAGRAM
CS1
CS0
DQS0
DM0/DQS9
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS4
DM4/DQS13
CS
DQS
U0
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS
CS DQS
U8
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U4
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U12
DQS1
DM1/DQS10
DM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS5
DM5/DQS14
CS
DQS
U1
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U9
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U5
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U13
DQS2
DM2/DQS11
DM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS6
DM6/DQS15
CS
DQS
U2
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U10
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U6
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U14
DQS3
DM3/DQS12
DM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
DQS7
DM7/DQS16
CS
DQS
U3
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U11
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U7
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
DQS
U15
A0 ~ A13, BA0 & 1
RAS
SERIAL PD
SCL
U7
A0
A1
A2
SDA
WP
WE
SA0
SA1
SA2
SDA
CKE0
V
DD
SPD
V
DD
/V
DDQ
CAS
SDRAMs U0 ~ U15
SDRAMs U0 ~ U15
SDRAMs U0 ~ U15
SDRAMs U0 ~ U15
CKE1
SDRAMs U8 ~ U15
SDRAMs U0 ~ U7
SPD
D0~D15
V
REF
V
SS
D0~D15
D0~D15
V
DDID
-4-
W9451GBDA
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation for Each Component
Short Circuit Output Current
SYMBOL
V
IN,
V
OUT
V
DD
, V
DDQ
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
RATING
-0.3
−
V
DDQ
+0.3
-0.3
−
3.6
0
−
70
-55
−
150
260
16
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
8. RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to 70
°C)
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input reference Voltage
Termination Voltage (System)
Input High Voltage (DC)
Input Low Voltage (DC)
Differential Clock DC Input Voltage
Input Differential Voltage. CLK and
CLK
inputs (DC)
SYMBOL
V
DD
V
DDQ
V
REF
V
TT
V
IH (DC)
V
IL (DC)
V
ICK (DC
)
V
ID (DC)
V
IH (AC)
V
IL (AC)
V
ID (AC)
VX
(AC)
V
ISO (AC)
MIN.
2.3
2.3
0.49 x V
DDQ
V
REF
-0.04
V
REF
+0.15
-0.3
-0.1
0.36
V
REF
+0.31
-
0.7
V
DDQ
/2 -0.2
V
DDQ
/2 -0.2
TYP.
2.5
2.5
0.50 x V
DDQ
V
REF
-
-
-
-
-
-
-
-
-
MAX.
2.7
V
DD
0.51 x V
DDQ
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.1
V
DDQ
+0.6
-
V
REF
-0.31
V
DDQ
+0.6
V
DDQ
/2 +0.2
V
DDQ
/2 +0.2
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
NOTES
2
2
2, 3
2
2
2
16
14, 16
2
2
14, 16
13, 16
15, 16
Input High Voltage (AC)
Input Low Voltage (AC)
Input Differential Voltage. CLK and
CLK
inputs (AC)
Differential AC input Cross Point
Voltage
Differential Clock AC Middle Point
Notes: Undershoot limit: V
IL
(min.) = -0.9V with a pulse width < 5 nS
Overshoot limit: V
IH
(max.) = V
DD
Q +0.9V with a pulse width < 5 nS
V
IH(DC)
and V
IL(DC)
are levels to maintain the current logic state, V
IH(AC)
and V
IL(AC)
are levels to change to the new logic
state.
-5-
Publication Release Date: March 15, 2002
Revision A1
