W948D6FB / W948D2FB
256Mb Mobile LPDDR
TABLE OF CONTENTS
1. GENERAL DESCRIPTION .................................................................................................. 4
2. FEATURES.......................................................................................................................... 4
3. PIN CONFIGURATION ........................................................................................................ 5
3.1 Ball Assignment: LPDDR x16 ..................................................................................................... 5
3.2 Ball Assignment: LPDDR x32 ..................................................................................................... 5
4. PIN DESCRIPTION ............................................................................................................. 6
4.1 Signal Descriptions ..................................................................................................................... 6
4.2 Addressing Table ........................................................................................................................ 7
5. BLOCK DIAGRAM .............................................................................................................. 8
5.1 Block Diagram ............................................................................................................................ 8
5.2 Simplified State Diagram ............................................................................................................ 9
6. FUNCTION DESCRIPTION ............................................................................................... 10
6.1 Initialization ............................................................................................................................... 10
6.1.1 Initialization Flow Diagram ............................................................................................................. 11
6.1.2 Initialization Waveform Sequence ................................................................................................. 12
6.2 Register Definition .................................................................................................................... 12
6.2.1 Mode Register Set Operation ........................................................................................................ 12
6.2.2 Mode Register Definition ............................................................................................................... 13
6.2.3. Burst Length ................................................................................................................................. 13
6.3 Burst Definition ......................................................................................................................... 14
6.4 Burst Type ................................................................................................................................ 15
6.5 Read Latency............................................................................................................................ 15
6.6 Extended Mode Register Description ....................................................................................... 15
6.6.1 Extended Mode Register Definition ............................................................................................... 16
6.7 Status Register Read ................................................................................................................ 16
6.7.1 SRR Register (A[n:0] = 0) .............................................................................................................. 17
6.7.2 Status Register Read Timing Diagram .......................................................................................... 18
6.8 Partial Array Self Refresh ......................................................................................................... 19
6.9 Automatic Temperature Compensated Self Refresh ................................................................ 19
6.10 Output Drive Strength ............................................................................................................. 19
6.11 Commands ............................................................................................................................. 19
6.11.1 Basic Timing Parameters for Commands .................................................................................... 19
6.11.2 Truth Table - Commands ............................................................................................................. 20
6.11.3 Truth Table - DM Operations ....................................................................................................... 21
6.11.4 Truth Table - CKE ........................................................................................................................ 21
6.11.5 Truth Table - Current State BANKn - Command to BANKn ........................................................ 22
6.11.6 Truth Table - Current State BANKn, Command to BANKn ......................................................... 23
7. OPERATION...................................................................................................................... 24
7.1. Deselect ................................................................................................................................... 24
7.2. No Operation ........................................................................................................................... 24
7.2.1 NOP Command ............................................................................................................................. 25
7.3 Mode Register Set .................................................................................................................... 25
Publication Release Date : Oct, 15, 2012
Revision : A01-004
-1-
W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.3.1 Mode Register Set Command ....................................................................................................... 25
7.3.2 Mode Register Set Command Timing ........................................................................................... 26
7.4. Active ....................................................................................................................................... 26
7.4.1 Active Command ........................................................................................................................... 26
7.4.2 Bank Activation Command Cycle .................................................................................................. 27
7.5. Read ........................................................................................................................................ 27
7.5.1 Read Command............................................................................................................................. 28
7.5.2 Basic Read Timing Parameters ..................................................................................................... 28
7.5.3 Read Burst Showing CAS Latency ................................................................................................ 29
7.5.4 Read to Read................................................................................................................................. 29
7.5.5 Consecutive Read Bursts .............................................................................................................. 30
7.5.6 Non-Consecutive Read Bursts ...................................................................................................... 30
7.5.7 Random Read Bursts .................................................................................................................... 31
7.5.8 Read Burst Terminate.................................................................................................................... 31
7.5.9 Read to Write ................................................................................................................................. 32
7.5.10 Read to Pre-charge ..................................................................................................................... 32
7.6 Write ......................................................................................................................................... 33
7.6.1 Write Command ............................................................................................................................. 34
7.6.2 Basic Write Timing Parameters ..................................................................................................... 34
7.6.3 Write Burst (min. and max. tDQSS)............................................................................................... 35
7.6.4 Write to Write ................................................................................................................................. 35
7.6.5 Concatenated Write Bursts ............................................................................................................ 36
7.6.6 Non-Consecutive Write Bursts ...................................................................................................... 36
7.6.7 Random Write Cycles .................................................................................................................... 37
7.6.8 Write to Read ................................................................................................................................. 37
7.6.9 Non-Interrupting Write to Read ...................................................................................................... 37
7.6.10 Interrupting Write to Read ........................................................................................................... 38
7.6.11 Write to Precharge ....................................................................................................................... 38
7.6.12 Non-Interrupting Write to Precharge............................................................................................ 38
7.6.13 Interrupting Write to Precharge ................................................................................................... 39
7.7 Precharge ................................................................................................................................. 39
7.7.1 Precharge Command..................................................................................................................... 40
7.8 Auto Precharge ......................................................................................................................... 40
7.9 Refresh Requirements .............................................................................................................. 40
7.10 Auto Refresh ........................................................................................................................... 40
7.10.1 Auto Refresh Command .............................................................................................................. 41
7.11 Self Referesh .......................................................................................................................... 41
7.11.1 Self Refresh Command ............................................................................................................... 42
7.11.2 Auto Refresh Cycles Back-to-Back ............................................................................................. 42
7.11.3 Self Refresh Entry and Exit ......................................................................................................... 43
7.12 Power Down ........................................................................................................................... 43
7.12.1 Power-Down Entry and Exit ......................................................................................................... 43
7.13 Deep Power Down .................................................................................................................. 44
7.13.1 Deep Power-Down Entry and Exit ............................................................................................... 44
7.14 Clock Stop .............................................................................................................................. 45
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Publication Release Date : Oct, 15, 2012
Revision : A01-004
W948D6FB / W948D2FB
256Mb Mobile LPDDR
7.14.1 Clock Stop Mode Entry and Exit .................................................................................................. 45
8. ELECTRICAL CHARACTERISTIC ................................................................................... 46
8.1 Absolute Maximum Ratings ...................................................................................................... 46
8.2 Input/Output Capacitance ......................................................................................................... 46
8.3 Electrical Characteristics and AC/DC Operating Conditions .................................................... 47
8.3.1 Electrical Characteristics and AC/DC Operating Conditions ......................................................... 47
8.4 IDD Specification Parameters and Test Conditions .................................................................. 48
8.4.1 IDD Specification Parameters and Test Conditions ...................................................................... 48
8.5 AC Timings ............................................................................................................................... 51
8.5.1 CAS Latency Definition (With CL=3) ............................................................................................. 54
8.5.2 Output Slew Rate Characteristics.................................................................................................. 55
8.5.3 AC Overshoot/Undershoot Specification ....................................................................................... 55
8.5.4 AC Overshoot and Undershoot Definition ..................................................................................... 55
9. PACKAGE DIMENSIONS ................................................................................................. 56
9.1: LPDDR X 16 ............................................................................................................................ 56
9.2: LPDDR X 32 ............................................................................................................................ 57
10. ORDERING INFORMATION ........................................................................................... 58
11. REVISION HISTORY ....................................................................................................... 59
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Publication Release Date : Oct, 15, 2012
Revision : A01-004
W948D6FB / W948D2FB
256Mb Mobile LPDDR
1. GENERAL DESCRIPTION
W948D6FB / W948D2FB is a high-speed Low Power double data rate synchronous dynamic random access
memory (LPDDR SDRAM), An access to the LPDDR SDRAM is burst oriented. Consecutive memory location in one
page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is selected by an ACTIVE command.
Column addresses are automatically generated by the LPDDR SDRAM internal counter in burst operation. Random
column read is also possible by providing its address at each clock cycle. The multiple bank nature enables
interleaving among internal banks to hide the pre-charging time. By setting programmable Mode Registers, the
system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. The
device supports special power saving functions such as Partial Array Self Refresh (PASR) and Automatic
Temperature Compensated Self Refresh (ATCSR).
2. FEATURES
VDD = 1.7~1.95V
VDDQ = 1.7~1.95V
Data width: x16 / x32
Clock rate: 200MHz(-5),166MHz (-6), 133MHz (-75)
Partial Array Self-Refresh(PASR)
Auto Temperature Compensated Self-Refresh(ATCSR)
Power Down Mode
Deep Power Down Mode (DPD Mode)
Programmable output buffer driver strength
Four internal banks for concurrent operation
Data mask (DM) for write data
Clock Stop capability during idle periods
Auto Pre-charge option for each burst access
Double data rate for data output
CAS
Latency: 2 and 3
Burst Length: 2, 4, 8 and 16
Burst Type: Sequential or Interleave
64 ms Refresh period
Interface: LVCMOS
Support package:
60 balls VFBGA (x16)
90 balls VFBGA (x32)
Operating Temperature Range
Extended (-25°C to + 85 °C)
Industrial (-40°C to + 85 °C)
Differential clock inputs (CK and
CK
)
Bidirectional, data strobe (DQS)
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Publication Release Date : Oct, 15, 2012
Revision : A01-004
W948D6FB / W948D2FB
256Mb Mobile LPDDR
3. PIN CONFIGURATION
3.1 Ball Assignment: LPDDR x16
60 BALL
1
A
B
C
D
E
F
G
H
J
K
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CKE
A9
A6
VSS
2
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CK
A11
A7
A4
3
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
CK
VFBGA
5
6
7
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
WE
4
8
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
CAS
9
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VDD
RAS
A12
A8
A5
CS
BA0
A0
A3
BA1
A1
VDD
A10/AP
A2
(Top View) Pin Configuration
3.2 Ball Assignment: LPDDR x32
90 BALL
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
CKE
A9
A6
A4
VSSQ
VDDQ
VSSQ
VDDQ
VSS
2
DQ31
DQ29
DQ27
DQ25
DQS3
DM3
CK
A11
A7
DM1
DQS1
DQ9
DQ11
DQ13
DQ15
3
VSSQ
DQ30
DQ28
DQ26
DQ24
NC
CK
VFBGA
5
6
7
VDDQ
DQ17
DQ19
DQ21
DQ23
NC
WE
4
8
DQ16
DQ18
DQ20
DQ22
DQS2
DM2
CAS
9
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSS
RAS
NC
A8
A5
DQ8
DQ10
DQ12
DQ14
VSSQ
CS
BA0
A0
DM0
DQS0
DQ6
DQ4
DQ2
DQ0
BA1
A1
A3
VDDQ
VSSQ
VDDQ
VSSQ
VDD
A10/AP
A2
DQ7
DQ5
DQ3
DQ1
VDDQ
(Top View) Pin Configuration
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Publication Release Date : Oct, 15, 2012
Revision : A01-004
