W948V6KBHX
256Mb Mobile LPDDR
Table of Contents-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ................................................................................................................................. 4
FEATURES ........................................................................................................................................................ 4
ORDER INFORMATION .................................................................................................................................... 4
BALL ASSIGNMENT .......................................................................................................................................... 5
BALL CONFIGURATION .................................................................................................................................... 6
5.1
Ball Descriptions ................................................................................................................................... 6
5.2
Addressing Table ................................................................................................................................. 7
6. BLOCK DIAGRAM.............................................................................................................................................. 8
6.1
Block Diagram ...................................................................................................................................... 8
6.2
Simplified State Diagram ...................................................................................................................... 9
7. FUNCTIONAL DESCRIPTION ......................................................................................................................... 10
7.1
Initialization......................................................................................................................................... 10
7.1.1
Initialization Flow Diagram.................................................................................................... 11
7.1.2
Initialization Waveform Sequence ........................................................................................ 12
7.2
Mode Register Set Operation ............................................................................................................. 12
7.3
Mode Register Definition .................................................................................................................... 13
7.3.1
Burst Length ......................................................................................................................... 13
7.3.2
Burst Definition ..................................................................................................................... 14
7.3.3
Burst Type ............................................................................................................................ 15
7.3.4
Read Latency ....................................................................................................................... 15
7.4
Extended Mode Register Description ................................................................................................. 15
7.4.1
Extended Mode Register Definition ...................................................................................... 16
7.4.2
Partial Array Self Refresh ..................................................................................................... 16
7.4.3
Automatic Temperature Compensated Self Refresh ............................................................ 16
7.4.4
Output Drive Strength ........................................................................................................... 16
7.5
Status Register Read ......................................................................................................................... 17
7.5.1
SRR Register Definition........................................................................................................ 17
7.5.2
Status Register Read Timing Diagram ................................................................................. 18
7.6
Commands ......................................................................................................................................... 19
7.6.1
Basic Timing Parameters for Commands ............................................................................. 19
7.6.2
Truth Table – Commands ..................................................................................................... 19
7.6.3
Truth Table - DM Operations ................................................................................................ 20
7.6.4
Truth Table – CKE................................................................................................................ 20
7.6.5
Truth Table - Current State Bank n - Command to Bank n ................................................... 21
7.6.6
Truth Table - Current State Bank n, Command to Bank m ................................................... 22
8. OPERATION .................................................................................................................................................... 24
8.1
Deselect ............................................................................................................................................. 24
8.2
No Operation ...................................................................................................................................... 24
8.2.1
NOP Command .................................................................................................................... 24
8.3
Mode Register Set .............................................................................................................................. 25
8.3.1
Mode Register Set Command .............................................................................................. 25
8.3.2
Mode Register Set Command Timing .................................................................................. 25
8.4
Active.................................................................................................................................................. 26
8.4.1
Active Command .................................................................................................................. 26
8.4.2
Bank Activation Command Cycle ......................................................................................... 27
Publication Release Date: Jun. 04, 2018
Revision: A01-002
-1-
W948V6KBHX
Read ................................................................................................................................................... 27
8.5.1
Read Command ................................................................................................................... 27
8.5.2
Basic Read Timing Parameters ............................................................................................ 28
8.5.3
Read Burst Showing CAS Latency ....................................................................................... 29
8.5.4
Read to Read ....................................................................................................................... 29
8.5.5
Consecutive Read Bursts ..................................................................................................... 29
8.5.6
Non-Consecutive Read Bursts ............................................................................................. 30
8.5.7
Random Read Bursts ........................................................................................................... 31
8.5.8
Read Burst Terminate .......................................................................................................... 31
8.5.9
Read to Write ....................................................................................................................... 32
8.5.10 Read to Precharge ............................................................................................................... 33
8.5.11 Burst Terminate of Read ...................................................................................................... 34
8.6
Write ................................................................................................................................................... 34
8.6.1
Write Command ................................................................................................................... 34
8.6.2
Basic Write Timing Parameters ............................................................................................ 35
8.6.3
Write Burst (min. and max. tDQSS) ...................................................................................... 36
8.6.4
Write to Write........................................................................................................................ 36
8.6.5
Concatenated Write Bursts................................................................................................... 37
8.6.6
Non-Concatenated Write Bursts ........................................................................................... 37
8.6.7
Random Write Cycles ........................................................................................................... 38
8.6.8
Write to Read ....................................................................................................................... 38
8.6.9
Non-Interrupting Write to Read ............................................................................................. 38
8.6.10 Interrupting Write to Read .................................................................................................... 39
8.6.11 Write to Precharge ............................................................................................................... 39
8.6.12 Non-Interrupting Write to Precharge ..................................................................................... 39
8.6.13 Interrupting Write to Precharge ............................................................................................ 40
8.7
Precharge ........................................................................................................................................... 40
8.7.1
Precharge Command ........................................................................................................... 41
8.8
Auto Precharge .................................................................................................................................. 41
8.9
Refresh Requirements........................................................................................................................ 41
8.10 Auto Refresh ...................................................................................................................................... 42
8.10.1 Auto Refresh Command ....................................................................................................... 42
8.10.2 Auto Refresh Cycles Back-to-Back ...................................................................................... 42
8.11 Self Refresh........................................................................................................................................ 43
8.11.1 Self Refresh Command ........................................................................................................ 43
8.11.2 Deep power down quarter partial array Self Refresh (DSR) / Self Refresh Entry and Exit ... 44
8.12 Power Down ....................................................................................................................................... 45
8.12.1 Power-Down Entry and Exit.................................................................................................. 45
8.13 Deep Power Down.............................................................................................................................. 46
8.13.1 Deep Power-Down Entry and Exit ........................................................................................ 46
8.14 Clock Stop .......................................................................................................................................... 47
8.14.1 Clock Stop Mode Entry and Exit ........................................................................................... 47
9. ELECTRICAL CHARACTERISTICS ................................................................................................................. 48
9.1
Absolute Maximum Ratings ................................................................................................................ 48
9.2
Input / Output Capacitance ................................................................................................................. 48
9.3
Electrical Characteristics and AC/DC Operating Conditions ............................................................... 49
9.3.1
Electrical Characteristics and AC/DC Operating Conditions................................................. 49
8.5
Publication Release Date: Jun. 04, 2018
Revision: A01-002
-2-
W948V6KBHX
DC Characteristics.............................................................................................................................. 50
9.4.1
IDD Specification and Test Conditions ................................................................................. 50
9.5
AC Characteristics and Operating Condition ...................................................................................... 52
9.5.1
CAS Latency Definition (With CL = 3) .................................................................................. 54
9.5.2
Output Slew Rate Characteristics ......................................................................................... 55
9.5.3
AC Overshoot/Undershoot Specification .............................................................................. 55
9.5.4
AC Overshoot and Undershoot Definition............................................................................. 55
10. PACKAGE DIMENSIONS ................................................................................................................................ 56
11. REVISION HISTORY ....................................................................................................................................... 57
9.4
Publication Release Date: Jun. 04, 2018
Revision: A01-002
-3-
W948V6KBHX
1. GENERAL DESCRIPTION
W948V6KBHX is a high-speed Low Power double data rate synchronous dynamic random access
memory (LPDDR SDRAM), an access to the LPDDR SDRAM is burst oriented. Consecutive memory
location in one page can be accessed at a burst length of 2, 4, 8 and 16 when a bank and row is
selected by an ACTIVE command. Column addresses are automatically generated by the LPDDR
SDRAM internal counter in burst operation. Random column read is also possible by providing its
address at each clock cycle. The multiple bank nature enables interleaving among internal banks to
hide the pre-charging time. By setting programmable Mode Registers, the system can change burst
length, latency cycle, interleave or sequential burst to maximize its performance. The device supports
special low power functions such as Partial Array Self Refresh (PASR) and Automatic Temperature
Compensated Self Refresh (ATCSR).
2. FEATURES
V
DD
= 1.7~1.95V
V
DDQ
= 1.7~1.95V
Data width: x16
Clock rate: 200MHz (-5),166MHz (-6)
Standard Self Refresh Mode
Partial Array Self-Refresh(PASR)
Auto Temperature Compensated Self Refresh
(ATCSR)
Power Down Mode
Deep Power Down Mode (DPD Mode)
Deep power down quarter partial array Self
Refresh Mode (DSR Mode)
Programmable output buffer driver strength
Four internal banks for concurrent operation
Data mask (DM) for write data
Clock Stop capability during idle periods
Auto Pre-charge option for each burst access
Double data rate for data output
Differential clock inputs (CK and
CK
)
Bidirectional, data strobe (DQS)
CAS
Latency: 2 and 3
Burst Length: 2, 4, 8 and 16
Burst Type: Sequential or Interleave
8K refresh cycles/64 mS
Interface: LVCMOS compatible
Support package:
60 balls VFBGA
Operating Temperature Range:
Extended: -25°C ≤ T
CASE
≤ 85°C
Industrial: -40°C ≤ T
CASE
≤ 85°C
3. ORDER INFORMATION
PART NUMBER
W948V6KBHX5E
W948V6KBHX5I
W948V6KBHX6E
W948V6KBHX6I
V
DD
/V
DDQ
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
1.8V/1.8V
I/O WIDTH
16
16
16
16
TYPE
60VFBGA
60VFBGA
60VFBGA
60VFBGA
OTHERS
200MHz, -25°C~85°C
200MHz, -40°C~85°C
166MHz, -25°C~85°C
166MHz, -40°C~85°C
Publication Release Date: Jun. 04, 2018
Revision: A01-002
-4-
W948V6KBHX
4. BALL ASSIGNMENT
60 BALL VFBGA
3
4 5 6
V
SSQ
DQ14
DQ12
DQ10
DQ8
NC
CK
A
B
C
D
E
F
G
H
J
K
1
V
SS
V
DDQ
V
SSQ
V
DDQ
V
SSQ
VSS
CKE
A9
A6
V
SS
2
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CK
A11
A7
A4
7
V
DDQ
DQ1
DQ3
DQ5
DQ7
NC
8
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
CAS
9
V
DD
V
SSQ
V
DDQ
V
SSQ
V
DDQ
V
DD
RAS
WE
CS
A12
A8
A5
BA0
A0
A3
BA1
A1
V
DD
A10/AP
A2
(Top View) Ball Configuration
Publication Release Date: Jun. 04, 2018
Revision: A01-002
-5-
