W964A6BBN
1M WORD
×
16 BIT LOW POWER PSEUDO SRAM
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. PRODUCT OPTIONS ......................................................................................................................... 3
5. BALL DESCRIPTION .......................................................................................................................... 4
6. BLOCK DIAGRAM .............................................................................................................................. 5
7. FUNCTION TRUTH TABLE ................................................................................................................ 6
8. ELECTRICAL CHARACTERISTICS ................................................................................................... 7
Absolute Maximum Ratings .............................................................................................................. 7
Recommended Operation Conditions............................................................................................... 7
Capacitance ...................................................................................................................................... 8
DC Characteristics ............................................................................................................................ 8
AC Characteristics ............................................................................................................................ 9
Read Operation ..........................................................................................................................................9
Write Operation.........................................................................................................................................11
Power Down and Power Down Program Parameters ...............................................................................13
Other Timing Parameters .........................................................................................................................13
AC Test Conditions...................................................................................................................................13
9. TIMING WAVEFORMS ..................................................................................................................... 14
Read Timing #1 (
OE
Control Access)............................................................................................ 14
Read Timing #2 (
CE1
Control Access) .......................................................................................... 15
Read Timing #3 (Address Access after
OE
Control Access) ........................................................ 16
Read Timing #4 (Address Access after
CE1
Control Access) ....................................................... 17
Write Timing #1 (
CE1
Control) ....................................................................................................... 18
Write Timing #2-1 (
WE
Control, Single Write Operation) .............................................................. 19
Write Timing #2 (
WE
Control, Continuous Write Operation) ......................................................... 20
Read/Write Timing #1-1 (
CE1
Control)........................................................................................... 21
Read/Write Timing #1-2 (
CE1
Control)........................................................................................... 22
-1-
Publication Release Date: March 20, 2003
Revision A1
W964A6BBN
Read (
OE
Control) / Write (
WE
Control) Timing #2-1 .................................................................. 23
Read (
OE
Control) / Write (
WE
Control) Timing #2-2 .................................................................. 24
Power Down Program Timing ......................................................................................................... 25
Power Down Entry and Exit Timing................................................................................................. 25
Power-up Timing #1 ........................................................................................................................ 25
Power-up Timing #2 ........................................................................................................................ 26
Standby Entry Timing after Read or Write ...................................................................................... 26
10. PACKAGE DIMENSION.................................................................................................................. 27
TFBGA 48 Balls (6 x 8 mm^2, pitch 0.75 mm)................................................................................ 27
11. ORDERING INFORMATION........................................................................................................... 28
12. VERSION HISTORY ....................................................................................................................... 29
-2-
W964A6BBN
1. GENERAL DESCRIPTION
W964A6BBN is a 16M bits CMOS pseudo static random access memory (Pseudo SRAM), organized
as 1M words x 16 bits. Using advanced single transistor DRAM architecture and 0.175
µm
process
technology; W964A6BBN delivers fast access cycle time and low power consumption. It is suitable for
mobile device application such as Cellular Phone and PDA, which high-density buffer is needed and
power dissipation is most concerned
2. FEATURES
•
Asynchronous SRAM interface
•
Fast access cycle time:
•
Power supply:
−
V
DD
= +2.3V to +3.3V
•
Temperature:
−
t
RC
= 70 nS (-70), 80 nS (-80)
•
Low power consumption:
−
T
A
= 0°C to +70°C
−
T
A
= -25°C to +85°C (Extended temperature)
−
T
A
= -40°C to +85°C (Industrial temperature)
−
I
DDA1
= 20 mA Max.
−
I
DDS1
= 70
µA
Max.
•
Byte write control
3. PRODUCT OPTIONS
PARAMETER
W964A6BBN70
W964A6BBN80
t
RC
I
DDS1
I
DDA1
V
DD
70 nS Min.
70
µA
Max.
20 mA
2.3V to 2.7V
80 nS Min.
70
µA
Max.
20 mA
2.3V to 3.3V
-3-
Publication Release Date: March 20, 2003
Revision A1
W964A6BBN
4. BALL CONFIGURATION
Top view
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
CE2
B
DQ9
UB
A3
A4
CE1
DQ1
C
DQ10
DQ11
A5
A6
DQ2
DQ3
D
V
SS
DQ12
A17
A7
DQ4
V
DD
E
V
DD
DQ13
NC
A16
DQ5
V
SS
F
DQ15
DQ14
A14
A15
DQ6
DQ7
G
DQ16
A19
A12
A13
WE
DQ8
H
A18
A8
A9
A10
A11
NC
( FBGA48 , 6 x 8mm , pitch 0.75mm )
5. BALL DESCRIPTION
SYMBOL
DESCRIPTION
A0
−
A19
CE1
Address Input
Chip Enable Input 1, Low: Enable
Chip Enable Input 2, High: Enable, Low: Enter Power Down Mode
Write Enable Input
Output Enable Input
Lower Byte Write Control
Upper Byte Write Control
Data Inputs/Outputs
Power Supply
Ground
No Connection
CE2
WE
OE
LB
UB
I/O0
−
I/O15
V
DD
V
SS
NC
-4-
W964A6BBN
6. BLOCK DIAGRAM
V
DD
V
SS
A0
to
A18
ADDRESS
LATCH &
BUFFER
MEMORY
CELL
ARRAY
33,554,432 bits
ROW
DECODER
DQ1
to
DQ8
DQ9
to
DQ16
INPUT /
OUTPUT
BUFFER
INPUT DATA
LATCH &
CONTROL
SENSE /
SWITCH
COLUMN /
DECODER
OUTPUT
DATA
CONTROL
ADDRESS
LATCH &
BUFFER
CE2
PE
CE1
WE
LB
UB
OE
POWER
CONTROL
TIMING
CONTROL
-5-
Publication Release Date: March 20, 2003
Revision A1
