W972GG6JB
16M
8 BANKS
16 BIT DDR2 SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
7.1
7.2
GENERAL DESCRIPTION ................................................................................................................... 4
FEATURES ........................................................................................................................................... 4
KEY PARAMETERS ............................................................................................................................. 5
BALL CONFIGURATION ...................................................................................................................... 6
BALL DESCRIPTION ............................................................................................................................ 7
BLOCK DIAGRAM ................................................................................................................................ 8
FUNCTIONAL DESCRIPTION .............................................................................................................. 9
Power-up and Initialization Sequence ................................................................................................... 9
Mode Register and Extended Mode Registers Operation ................................................................... 10
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
7.2.4
7.2.5
7.2.5.1
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.4
Mode Register Set Command (MRS)............................................................................... 10
Extend Mode Register Set Commands (EMRS) .............................................................. 11
Extend Mode Register Set Command (1), EMR (1)................................................ 11
DLL Enable/Disable ................................................................................................ 12
Extend Mode Register Set Command (2), EMR (2) ................................................ 13
Extend Mode Register Set Command (3), EMR (3) ................................................ 14
Off-Chip Driver (OCD) Impedance Adjustment ................................................................ 15
Extended Mode Register for OCD Impedance Adjustment .................................... 16
OCD Impedance Adjust .......................................................................................... 16
Drive Mode ............................................................................................................. 17
On-Die Termination (ODT) ............................................................................................... 18
ODT related timings ......................................................................................................... 18
MRS command to ODT update delay ..................................................................... 18
Bank Activate Command.................................................................................................. 20
Read Command ............................................................................................................... 21
Write Command ............................................................................................................... 21
Burst Read with Auto-precharge Command..................................................................... 21
Burst Write with Auto-precharge Command ..................................................................... 21
Precharge All Command .................................................................................................. 21
Self Refresh Entry Command .......................................................................................... 21
Self Refresh Exit Command ............................................................................................. 22
Refresh Command ........................................................................................................... 22
No-Operation Command .................................................................................................. 23
Device Deselect Command .............................................................................................. 23
Command Function ............................................................................................................................. 20
Read and Write access modes ........................................................................................................... 23
7.4.1
Posted
CAS
.................................................................................................................... 23
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Publication Release Date: Nov. 29, 2011
Revision A02
W972GG6JB
7.4.1.1
7.4.2
7.4.3
7.4.4
7.4.5
7.5
7.6
Examples of posted
CAS
operation ..................................................................... 23
Burst mode operation ....................................................................................................... 24
Burst read mode operation ............................................................................................... 25
Burst write mode operation .............................................................................................. 25
Write data mask ............................................................................................................... 26
Burst Interrupt ..................................................................................................................................... 26
Precharge operation............................................................................................................................ 27
7.6.1
7.6.2
Burst read operation followed by precharge ..................................................................... 27
Burst write operation followed by precharge .................................................................... 27
Burst read with Auto-precharge ....................................................................................... 28
Burst write with Auto-precharge ....................................................................................... 28
7.7
Auto-precharge operation ................................................................................................................... 27
7.7.1
7.7.2
7.8
7.9
Refresh Operation ............................................................................................................................... 29
Power Down Mode .............................................................................................................................. 29
7.9.1
7.9.2
Power Down Entry ........................................................................................................... 30
Power Down Exit .............................................................................................................. 30
7.10
8.
8.1
8.2
8.3
8.4
8.5
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
Input clock frequency change during precharge power down ............................................................. 30
OPERATION MODE ........................................................................................................................... 31
Command Truth Table ........................................................................................................................ 31
Clock Enable (CKE) Truth Table for Synchronous Transitions ........................................................... 32
Data Mask (DM) Truth Table ............................................................................................................... 32
Function Truth Table ........................................................................................................................... 33
Simplified Stated Diagram ................................................................................................................... 36
ELECTRICAL CHARACTERISTICS ................................................................................................... 37
Absolute Maximum Ratings ................................................................................................................ 37
Operating Temperature Condition ....................................................................................................... 37
Recommended DC Operating Conditions ........................................................................................... 38
ODT DC Electrical Characteristics ...................................................................................................... 38
Input DC Logic Level ........................................................................................................................... 38
Input AC Logic Level ........................................................................................................................... 38
Capacitance ........................................................................................................................................ 39
Leakage and Output Buffer Characteristics ........................................................................................ 39
DC Characteristics .............................................................................................................................. 40
IDD Measurement Test Parameters.................................................................................................... 42
AC Characteristics .............................................................................................................................. 43
9.11.1
9.11.2
AC Characteristics and Operating Condition for -18 speed grade ................................... 43
AC Characteristics and Operating Condition for -25/25I/25A/25K/-3/-3A speed grades .. 45
9.12
9.13
9.14
AC Input Test Conditions .................................................................................................................... 66
Differential Input/Output AC Logic Levels ........................................................................................... 66
AC Overshoot / Undershoot Specification ........................................................................................... 67
9.14.1
9.14.2
AC Overshoot / Undershoot Specification for Address and Control Pins: ........................ 67
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask pins: .......... 67
10.
TIMING WAVEFORMS ....................................................................................................................... 68
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Publication Release Date: Nov. 29, 2011
Revision A02
W972GG6JB
10.1 Command Input Timing ....................................................................................................................... 68
10.2 ODT Timing for Active/Standby Mode ................................................................................................. 69
10.3 ODT Timing for Power Down Mode .................................................................................................... 69
10.4 ODT Timing mode switch at entering power down mode .................................................................... 70
10.5 ODT Timing mode switch at exiting power down mode ...................................................................... 71
10.6 Data output (read) timing .................................................................................................................... 72
10.7 Burst read operation: RL=5 (AL=2, CL=3, BL=4) ................................................................................ 72
10.8 Data input (write) timing ...................................................................................................................... 73
10.9 Burst write operation: RL=5 (AL=2, CL=3, WL=4, BL=4) .................................................................... 73
10.10
Seamless burst read operation: RL = 5 ( AL = 2, and CL = 3, BL = 4) ...................................... 74
10.11
Seamless burst write operation: RL = 5 ( WL = 4, BL = 4)......................................................... 74
10.12
Burst read interrupt timing: RL =3 (CL=3, AL=0, BL=8) ............................................................. 75
10.13
Burst write interrupt timing: RL=3 (CL=3, AL=0, WL=2, BL=8) .................................................. 75
10.14
Write operation with Data Mask: WL=3, AL=0, BL=4) ............................................................... 76
10.15
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=4, tRTP ≤ 2clks) ............ 77
10.16
Burst read operation followed by precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............ 77
10.17
Burst read operation followed by precharge: RL=5 (AL=2, CL=3, BL=4, tRTP ≤ 2clks) ............ 78
10.18
Burst read operation followed by precharge: RL=6 (AL=2, CL=4, BL=4, tRTP ≤ 2clks) ............ 78
10.19
Burst read operation followed by precharge: RL=4 (AL=0, CL=4, BL=8, tRTP > 2clks) ............ 79
10.20
Burst write operation followed by precharge: WL = (RL-1) = 3 .................................................. 79
10.21
Burst write operation followed by precharge: WL = (RL-1) = 4 .................................................. 80
10.22
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=8, tRTP ≤ 2clks) ............... 80
10.23
Burst read operation with Auto-precharge: RL=4 (AL=1, CL=3, BL=4, tRTP > 2clks) ............... 81
10.24
Burst read with Auto-precharge followed by an activation to the same bank (tRC Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 81
10.25
Burst read with Auto-precharge followed by an activation to the same bank (tRP Limit): RL=5
(AL=2, CL=3, internal tRCD=3, BL=4, tRTP ≤ 2clks) ....................................................................................... 82
10.26
Burst write with Auto-precharge (tRC Limit): WL=2, WR=2, BL=4, tRP=3 ................................. 82
10.27
Burst write with Auto-precharge (WR + tRP Limit): WL=4, WR=2, BL=4, tRP=3 ....................... 83
10.28
Self Refresh Timing ................................................................................................................... 83
10.29
Active Power Down Mode Entry and Exit Timing ....................................................................... 84
10.30
Precharged Power Down Mode Entry and Exit Timing .............................................................. 84
10.31
Clock frequency change in precharge Power Down mode ........................................................ 85
11.
12.
PACKAGE SPECIFICATION .............................................................................................................. 86
Package Outline WBGA-84 (11x13 mm )........................................................................................................ 86
REVISION HISTORY .......................................................................................................................... 87
2
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Publication Release Date: Nov. 29, 2011
Revision A02
W972GG6JB
1. GENERAL DESCRIPTION
The W972GG6JB is a 2G bits DDR2 SDRAM, organized as 16,777,216 words
8 banks
16 bits.
This device achieves high speed transfer rates up to 1066Mb/sec/pin (DDR2-1066) for various
applications. W972GG6JB is sorted into the following grade parts: -18, -25, 25I, 25A, 25K, -3 and -3A.
The -18 is compliant to the DDR2-1066 (7-7-7) specification. The -25/25I/25A/25K are compliant to the
DDR2-800 (5-5-5) or DDR2-800 (6-6-6) specification (the 25I industrial grade parts is guaranteed to
support -40°C ≤ T
CASE
≤ 95°C). The -3/-3A are compliant to the DDR2-667 (5-5-5) specification.
The automotive grade parts temperature, if offered, has two simultaneous requirements: ambient
temperature (T
A
) surrounding the device cannot be less than -40°C or greater than +95°C (for 25A
and -3A), +105°C (for 25K), and the case temperature (T
CASE
) cannot be less than -40°C or greater
than +95°C (for 25A and -3A), +105°C (for 25K). JEDEC specifications require the refresh rate to
double when T
CASE
exceeds +85°C; this also requires use of the high-temperature self refresh option.
Additionally, ODT resistance and the input/output impedance must be derated when T
CASE
is < 0°C or
> +85°C.
All of the control and address inputs are synchronized with a pair of externally supplied differential
clocks. Inputs are latched at the cross point of differential clocks (CLK rising and
CLK
falling). All
I/Os are synchronized with a single ended DQS or differential DQS-
DQS
pair in a source
synchronous fashion.
2. FEATURES
Power Supply: V
DD
, V
DDQ
= 1.8 V
0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and
DQS
) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and
CLK
)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges
of DQS
Posted
CAS
programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal
quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
2
Packaged in WBGA 84 Ball (11X13 mm ), using Lead free materials with RoHS compliant
Publication Release Date: Nov. 29, 2011
Revision A02
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W972GG6JB
3. KEY PARAMETERS
SPEED GRADE
SYM.
Bin(CL-tRCD-tRP)
Part Number Extension
@CL = 7
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
DDR2-1066
7-7-7
-18
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
7.5 nS
3.75 nS
7.5 nS
13.125 nS
*
2
7.8 μS*
1
Max.
3.9 μS*
4
*
6
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
13.125 nS
58.125 nS
45 nS
90 mA
96 mA
195 mA
155 mA
175 mA
12 mA
310 mA
DDR2-800
5-5-5/6-6-6
-25/25I/25A/25K
2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
7.8 μS*
2, 3
7.8 μS*
1
3.9 μS*
4
3.9 μS*
5
12.5 nS
57.5 nS
45 nS
83 mA
91 mA
170 mA
150 mA
160 mA
12 mA
250 mA
DDR2-667
5-5-5
-3/-3A
3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
7.8 μS*
2, 3
7.8 μS*
1
3.9 μS*
4
*
6
15 nS
60 nS
45 nS
80 mA
86 mA
155 mA
140 mA
150 mA
12 mA
220 mA
@CL = 6
t
CK(avg)
Average clock period
@CL = 5
@CL = 4
@CL = 3
t
RCD
Active to Read/Write Command Delay Time
-40°C
≤
T
CASE
≤
85°C
t
REFI
Average periodic
refresh Interval
0°C
≤
T
CASE
≤
85°C
85°C
<
T
CASE
≤
95°C
95°C
<
T
CASE
≤
105°C
t
RP
t
RC
t
RAS
I
DD0
I
DD1
I
DD4R
I
DD4W
I
DD5B
I
DD6
I
DD7
Notes:
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating one bank active-precharge current
Operating one bank active-read-precharge
current
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (T
CASE
≤
85°C)
Operating bank interleave read current
All speed grades support 0°C
≤
T
CASE
≤
85°C with full JEDEC AC and DC specifications.
For -18, -25 and -3 speed grades, -40°C
≤
T
CASE
<
0°C is not available.
25I, 25A, 25K and -3A speed grades support -40°C
≤
T
CASE
≤
85°C with full JEDEC AC and DC specifications.
For all speed grade parts, T
CASE
is able to extend to 95°C with doubling Auto Refresh commands in frequency to a 32 mS
period ( t
REFI
= 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 "1" on EMR (2).
5. For 25K automotive speed grade, T
CASE
is able to extend to 105°C with doubling Auto Refresh commands in frequency to a
32 mS period ( t
REFI
= 3.9 µS) and to enter to Self Refresh mode at this high temperature range via A7 "1" on EMR (2).
6. For -18, -25, 25I, 25A, -3 and -3A speed grades, 95°C < T
CASE
≤ 105°C is not available.
1.
2.
3.
4.
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Publication Release Date: Nov. 29, 2011
Revision A02
