GENERAL DESCRIPTION ............................................................................................................................................ 6
FEATURES .................................................................................................................................................................... 6
ORDER INFORMATION ................................................................................................................................................ 7
Simplified LPDDR2 State Diagram .............................................................................................................................. 13
7.1.1
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
Simplified LPDDR2 Bus Interface State Diagram ......................................................................................................... 14
Power Ramp and Device Initialization.......................................................................................................................... 15
Timing Parameters for Initialization .............................................................................................................................. 17
Power Ramp and Initialization Sequence .................................................................................................................... 17
Initialization after Reset (without Power ramp) ............................................................................................................. 18
Burst Sequence by Burst Length (BL), Burst Type (BT), and Warp Control (WC) .............................................. 21
Non Wrap Restrictions ...................................................................................................................................... 21
Command Input Setup and Hold Timing............................................................................................................ 26
CKE Input Setup and Hold Timing .................................................................................................................... 26
Read and Write Access Modes.................................................................................................................................... 27
Reads Interrupted by a Read....................................................................................................................................... 32
Writes Interrupted by a Write ....................................................................................................................................... 35
Write Data Mask .......................................................................................................................................................... 37
Write Data Mask Timing .................................................................................................................................... 37
Bank Selection for Precharge by Address Bits .................................................................................................. 38
Burst Read Operation Followed by Precharge ............................................................................................................. 38
Burst Read Followed by Precharge: RL = 3, BL = 8, RU(tRTP(min)/tCK) = 2 .................................................... 39
Burst Read Followed by Precharge: RL = 3, BL = 4, RU(tRTP(min)/tCK) = 3 .................................................... 39
Burst Write Followed by Precharge ............................................................................................................................. 40
Auto Precharge Operation ........................................................................................................................................... 41
Burst Read with Auto-Precharge ................................................................................................................................. 41
Burst Write with Auto-Precharge.................................................................................................................................. 42
Definition of tSRF .............................................................................................................................................. 45
Allowable Transition from Repetitive Burst Refresh ........................................................................................... 47
NOT-Allowable Transition from Repetitive Burst Refresh .................................................................................. 47
Recommended Self-Refresh Entry and Exit ...................................................................................................... 48
All Bank Refresh Operation............................................................................................................................... 48
Burst Write Followed by MRR: RL = 3, WL = 1, BL = 4 ..................................................................................... 52
Temperature Sensor.................................................................................................................................................... 53
Temperature Sensor Timing ............................................................................................................................. 54
Refresh to Refresh Timing with CKE Intensive Environment ............................................................................. 61
Read to Power-Down Entry............................................................................................................................... 62
Read with Auto Precharge to Power-Down Entry .............................................................................................. 62
Write to Power-Down Entry ............................................................................................................................... 63
Write with Auto Precharge to Power-Down Entry .............................................................................................. 63
Refresh Command to Power-Down Entry.......................................................................................................... 64
Activate Command to Power-Down Entry ......................................................................................................... 64
Precharge/Precharge-All Command to Power-Down Entry ............................................................................... 64
Mode Register Read to Power-Down Entry ....................................................................................................... 65
MRW Command to Power-Down Entry ............................................................................................................. 65
Deep Power-Down ...................................................................................................................................................... 65
Deep Power Down Entry and Exit Timing.......................................................................................................... 66
Input Clock Stop and Frequency Change .................................................................................................................... 66
No Operation Command .............................................................................................................................................. 67
Command Truth Table................................................................................................................................................. 68
CKE Truth Table.......................................................................................................................................................... 69
Current State Bank n - Command to Bank n Truth Table ............................................................................................. 70
Current State Bank n - Command to Bank m Truth Table ............................................................................................ 72
Data Mask Truth Table ................................................................................................................................................ 73
7.5
Truth Tables ................................................................................................................................................................. 67
Absolute Maximum DC Ratings ................................................................................................................................... 74
AC & DC Operating Conditions .................................................................................................................................... 74
8.2.1
8.2.1.1
8.2.2
8.2.3
8.2.4
8.2.4.1
8.2.4.1.1
8.2.4.1.2
8.2.4.1.3
8.2.4.2
8.2.4.2.1
8.2.4.3
8.2.4.3.1
8.2.4.4
8.2.4.4.1
8.2.4.4.2
8.2.4.5
8.2.4.6
8.2.4.7
8.2.4.8
8.2.5
8.2.5.1
8.2.5.2
8.2.5.3
Recommended DC Operating Conditions .................................................................................................................... 74
Recommended DC Operating Conditions ......................................................................................................... 74
Input Leakage Current ................................................................................................................................................. 75
Operating Temperature Conditions .............................................................................................................................. 75
AC and DC Input Measurement Levels ........................................................................................................................ 75
AC and DC Logic Input Levels for Single-Ended Signals................................................................................... 75
Single-Ended AC and DC Input Levels for CA and CS_n Inputs ....................................................................... 75
Single-Ended AC and DC Input Levels for CKE ................................................................................................ 76
Single-Ended AC and DC Input Levels for DQ and DM ..................................................................................... 76
LPDDR2-800/1066 Input Signal ........................................................................................................................ 78
AC and DC Logic Input Levels for Differential Signals ....................................................................................... 79
Differential Signal Definition .............................................................................................................................. 79
Differential swing requirements for clock (CK_t - CK_c) and strobe (DQS_t - DQS_c) ...................................... 79
Single-Ended Requirements for Differential Signals .......................................................................................... 80
Differential Input Cross Point Voltage ................................................................................................................ 81
Slew Rate Definitions for Single-Ended Input Signals ....................................................................................... 82
Slew Rate Definitions for Differential Input Signals ............................................................................................ 82
AC and DC Output Measurement Levels ..................................................................................................................... 83
Single Ended AC and DC Output Levels ........................................................................................................... 83
Differential AC and DC Output Levels ............................................................................................................... 83
Single Ended Output Slew Rate ........................................................................................................................ 83
Definition of Switching for CA Input Signals ...................................................................................................... 93
Definition of Switching for IDD4R ...................................................................................................................... 94
Definition of Switching for IDD4W ..................................................................................................................... 94
Definition for tCK(avg) and nCK................................................................................................................................... 97
Definition for tCK(abs) ................................................................................................................................................. 97
Definition for tCH(avg) and tCL(avg) ............................................................................................................................ 98
Definition for tJIT(per) .................................................................................................................................................. 98
Definition for tJIT(cc) ................................................................................................................................................... 98
Definition for tERR(nper) ............................................................................................................................................. 98
Definition for Duty Cycle Jitter tJIT(duty) ...................................................................................................................... 99
Definition for tCK(abs), tCH(abs) and tCL(abs) ............................................................................................................ 99
Clock Period Jitter Effects on Core Timing Parameters ............................................................................................... 99
Cycle Time De-rating for Core Timing Parameters ............................................................................................ 99
Clock Cycle De-rating for Core Timing Parameters ......................................................................................... 100
Clock Jitter Effects on Command/Address Timing Parameters .................................................................................. 100
Clock Jitter Effects on Read Timing Parameters ........................................................................................................ 100
LPDDR2 AC Timing .................................................................................................................................................. 103
CA and CS_n Setup, Hold and Derating .................................................................................................................... 108
CA and CS_n Setup and Hold Base-Values for 1V/nS .................................................................................... 108
Derating Values LPDDR2 tIS/tIH - AC/DC Based AC220 ................................................................................ 109
Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition......................................................... 109
Nominal Slew Rate and tVAC for Setup Time tIS for CA and CS_n with Respect to Clock .............................. 110
Nominal Slew Rate for Hold Time tIH for CA and CS_n with Respect to Clock ................................................ 111
Tangent Line for Setup Time tIS for CA and CS_n with Respect to Clock ....................................................... 112
Tangent Line for Hold Time tIH for CA and CS_n with Respect to Clock ......................................................... 113
Data Setup, Hold and Slew Rate Derating ................................................................................................................. 114
Data Setup and Hold Base-Values .................................................................................................................. 114
8.3
IDD Specification Parameters and Test Conditions ..................................................................................................... 93
Period Clock Jitter ........................................................................................................................................................ 99
AC Timings ................................................................................................................................................................ 103
Publication Release Date: May 22, 2014
Revision: A01-001
-4-
W978H6KB / W978H2KB
8.7.3.2
8.7.3.3
8.7.3.4
8.7.3.5
8.7.3.6
8.7.3.7
Derating Values LPDDR2 tDS/tDH - AC/DC Based AC220 ............................................................................. 115
Required Time tVAC above VIH(ac) {below VIL(ac)} for Valid Transition......................................................... 115
Nominal Slew Rate and tVAC for Setup Time tDS for DQ with Respect to Strobe ........................................... 116
Nominal Slew Rate for Hold time tDH for DQ with Respect to Strobe .............................................................. 117
Tangent Line for Setup Time tDS for DQ with Respect to Strobe .................................................................... 118
Tangent Line for Hold Time tDH for DQ with Respect to Strobe ...................................................................... 119
REVISION HISTORY ................................................................................................................................................. 122
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