W981208AH
4M x 8 bit x 4 Banks SDRAM
Features
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3.3V
±
0.3V power supply
Up to 133MHz clock frequency
4,194,304 words x 4 banks x 8 bits organization
Auto Refresh and Self Refresh
CAS latency: 2 and 3
Burst Length: 1, 2, 4, 8 , and full page
Burst read, Single Writes Mode
Byte data controlled by DQM
Power-Down Mode
Auto-Precharge and controlled precharge
4k refresh cycles / 64ms
Interface: LVTTL
Package: TSOP II 54 pin, 400 mil - 0.80
General Description
W981208AH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 4M words x 4 banks x
8 bits. Using pipelined architecture and 0.20um process technology, W981208AH delivers a data bandwidth of up to 133M ( -
75) bytes per second. To fully comply to the personal computer industrial standard, W981208AH is sorted into two speed
grades: -75 and -8H. The -75 is compliant to the PC133 specitication, The -8H is compliant to the PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W981208AH is ideal for main memory in high performance applications.
Key Parameters
Symbol
t
CK
t
AC
t
RP
t
RCD
I
CC1
I
CC4
I
CC6
Description
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current ( Single bank )
Burst Operation Current
Self-Refresh Current
min/max
min
max
min
min
max
max
max
-75 (PC133)
7.5ns
5.4ns
20ns
20ns
85mA
120mA
2mA
-8H (PC100)
8ns
6ns
20ns
20ns
80mA
110mA
2mA
Revision 1.0
-1-
Publication Release Date: March, 1999
W981208AH
4M x 8 bit x 4 Banks SDRAM
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
DECODER
CONTROL
SIGNAL
GENERATOR
COMMAND
COLUMN DECODER
WE
ROW DECODER
ROW DECODER
COLUMN DECODER
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A0
ADDRESS
BUFFER
A9
A11
BS0
BS1
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DMn
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ7
REFRESH
COUNTER
COLUMN
COUNTER
DQM
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 4096 * 1024 * 8.
Revision 1.0
-2-
Publication Release Date: March, 1999
W981208AH
4M x 8 bit x 4 Banks SDRAM
Pin Assignment
Pin Number Pin Name
Function
23 ~ 26, 22,
A0~ A11
Address
29 ~35
20, 21
BS0, BS1
Bank Select
Data Input/
Output
Chip Select
Row Address
Strobe
Column Address
Strobe
Write Enable
Description
Multiplexed pins for row and column address.
Row address : A0 ~ A11. Column address: A0 ~ A9.
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
Referred to RAS#
2, 5, 8, 11,
DQ0 ~ DQ7
44, 47, 50, 53
19
18
17
16
39
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
CS#
RAS#
CAS#
WE#
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
Referred to RAS#
The output buffer is placed at Hi-Z(with latency of 2) when DQM
input/output mask is sampled high in read cycle. In write cycle, sampling DQM
high will block the write operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE
Clock Enable
is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
Power ( +3.3 V ) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power ( + 3.3 V ) Separated power from V
CC
, used for output buffers to improve
for I/O buffer
noise.
Ground for I/O
Separated ground from V
SS
, used for output buffers to improve
buffer
noise.
No Connection
No connection
4, 7, 10, 13,
15, 36, 40, 42, NC
45, 48, 51
Revision 1.0
-3-
Publication Release Date: March, 1999
W981208AH
4M x 8 bit x 4 Banks SDRAM
Pin Assignment (Top View)
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
Revision 1.0
-4-
Publication Release Date: March, 1999
W981208AH
4M x 8 bit x 4 Banks SDRAM
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
IN
,V
OUT
V
CC
,V
CC
Q
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
ITEM
Input, Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature(10s)
Power Dissipation
Short Circuit Output Current
RATING
-0.3~V
CC
+0.3
-0.3~4.6
0~70
-55~150
260
1
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70
°C
)
SYMBOL
V
CC
V
CC
Q
V
IH
V
IL
PARAMETER
Power Supply Voltage
Power Supply Voltage (for I/O Buffer)
Input High Voltage
Input Low Voltage
MIN
3.0
3.0
2.0
-0.3
TYP
3.3
3.3
-
-
MAX
3.6
3.6
V
CC
+0.3
0.8
UNIT
V
V
V
V
NOTES
2
2
2
2
Note:
V
IH
(max) = V
CC
/V
CC
Q+1.2V for pulse width < 5ns
V
IL
(min) = V
SS
/V
SS
Q-1.2V for pulse width < 5ns
CAPACITANCE (V
CC
=3.3V, f = 1MHz, Ta=25°C)
SYMBOL
C
I
C
O
PARAMETER
Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE)
Input Capacitance (CLK)
Input/Output capacitance
MIN
-
-
-
MAX
4
4
6.5
UNIT
pf
pf
pf
Note: These parameters are periodically sampled and not 100% tested.
Revision 1.0
-5-
Publication Release Date: March, 1999
