W981216BH
2M
×
4 BANKS
×
16 BIT SDRAM
GENERAL DESCRIPTION
W981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.175
µ
m process technology,
W981216BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W981216BH is sorted into three speed grades: -7, -75 and -
8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the
PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in
high performance applications.
FEATURES
•
3.3V
±
0.3V Power Supply
•
Up to 143 MHz Clock Frequency
•
2,097,152 Words
×
4 banks
×
16 bits organization
•
Auto Refresh and Self Refresh
•
CAS Latency: 2 and 3
•
Burst Length: 1, 2, 4, 8, and full page
•
Burst Read, Single Writes Mode
•
Byte Data Controlled by DQM
•
Power-Down Mode
•
Auto-precharge and Controlled Precharge
•
4K Refresh cycles / 64 mS
•
Interface: LVTTL
•
Packaged in TSOP II 54 pin, 400 mil - 0.80
KEY PARAMETERS
SYM.
DESCRIPTION
MIN.
/MAX.
-7
(PC133, CL2)
-75
(PC133, CL3)
-8H
(PC100)
t
CK
t
AC
t
RP
t
RCD
I
CC1
I
CC4
I
CC6
Clock Cycle Time
Access Time from CLK
Precharge to Active Command
Active to Read/Write Command
Operation Current (Single bank)
Burst Operation Current
Self-Refresh Current
Min.
Max.
Min.
Min.
Max.
Max.
Max.
7 nS
5.4 nS
15 nS
15 nS
80 mA
100 mA
2 mA
7.5 nS
5.4 nS
20 nS
20 nS
75 mA
95 mA
2 mA
8 nS
6 nS
20 nS
20 nS
70 mA
90 mA
2 mA
-1-
Publication Release Date: October 2000
Revision A1
W981216BH
PIN CONFIGURATION
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
-2-
W981216BH
PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
23
−
26, 22,
29
−
35
20, 21
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
19
A0
−
A11
Address
Multiplexed pins for row and column address.
Row address: A0
−
A11. Column address: A0
−
A8.
BS0, BS1
DQ0
−
DQ15
Bank Select
Data Input/
Output
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock, RAS , CAS and WE
operation to be executed.
Referred to RAS
Referred to RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
CC
, used for output buffers to
improve noise.
Separated ground from V
SS
, used for output buffers to
improve noise.
No connection
define the
18
RAS
Row Address
Strobe
17
16
39, 15
CAS
WE
Column Address
Strobe
Write Enable
Input/Output
Mask
UDQM/
LDQM
38
37
CLK
CKE
Clock Inputs
Clock Enable
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Power (+3.3V)
Ground
Power (+3.3V)
for I/O Buffer
Ground for I/O
Buffer
No Connection
-3-
Publication Release Date: October 2000
Revision A1
W981216BH
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
SIGNAL
GENERATOR
RAS
CAS
COMMAND
DECODER
COLUMN DECODER
COLUMN DECODER
R
O
W
WE
R
O
W
D
E
C
O
D
E
R
A10
CELL ARRAY
BANK #0
A0
ADDRESS
BUFFER
A9
A11
BS0
BS1
MODE
REGISTER
D
E
C
O
D
E
R
CELL ARRAY
BANK #1
SENSE AMPLIFIER
SENSE AMPLIFIER
DMn
DQ0
DATA CONTROL
CIRCUIT
REFRESH
COUNTER
COLUMN
COUNTER
DQ
BUFFER
DQ15
UDQM
LDQM
COLUMN DECODER
R
O
W
D
E
C
O
D
E
R
R
O
W
COLUMN DECODER
CELL ARRAY
BANK #2
D
C
O
D
E
R
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
Note: The cell array configuration is 4096 * 512 * 16.
-4-
W981216BH
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Input/Output Voltage
Power Supply Voltage
Operating Temperature
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
of the device.
V
IN,
V
OUT
V
CC
, V
CCQ
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
-0.3
−
V
CC
+0.3
-0.3
−
4.6
0
−
70
-55
−
150
260
1
50
V
V
°
C
°
C
°
C
W
mA
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= 0 to 70
°
C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Power Supply Voltage
Power Supply Voltage (for I/O
Buffer)
Input High Voltage
Input Low Voltage
Note: V
IH
(max) = V
CC
/ V
CC
Q+1.2V for pulse width < 5 nS
V
IL
(min) = V
SS
/ V
SS
Q-1.2V for pulse width < 5 nS
V
CC
V
CCQ
V
IH
V
IL
3.0
3.0
2.0
-0.3
3.3
3.3
-
-
3.6
3.6
V
CC
+0.3
0.8
V
V
V
V
CAPACITANCE
(V
CC
= 3.3V, f = 1 MHz, T
A
= 25
°
C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Input Capacitance
(A0 to A11, BS0, BS1, CS , RAS , CAS , WE , DQM,
CKE)
Input Capacitance (CLK)
Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested.
C
I
-
3.8
pf
C
CLK
C
IO
-
-
3.5
6.5
pf
pf
-5-
Publication Release Date: October 2000
Revision A1
