W9812G2IH
1M
×
4 BANKS
×
32BIT SDRAM
Table of Contents-
1
2
3
4
5
6
7
GENERAL DESCRIPTION .............................................................................................................. 3
FEATURES...................................................................................................................................... 3
AVAILABLE PART NUMBER .......................................................................................................... 3
PIN CONFIGURATION.................................................................................................................... 4
PIN DESCRIPTION ......................................................................................................................... 5
BLOCK DIAGRAM........................................................................................................................... 6
FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8
9
8.1
9.1
9.2
9.3
9.4
Power Up and Initialization.................................................................................................... 7
Programming Mode Register ................................................................................................ 7
Bank Activate Command ....................................................................................................... 7
Read and Write Access Modes ............................................................................................. 7
Burst Read Command ........................................................................................................... 8
Burst Write Command ........................................................................................................... 8
Read Interrupted by a Read .................................................................................................. 8
Read Interrupted by a Write .................................................................................................. 8
Write Interrupted by a Write .................................................................................................. 8
Write Interrupted by a Read .................................................................................................. 8
Burst Stop Command ............................................................................................................ 9
Addressing Sequence of Sequential Mode ........................................................................... 9
Addressing Sequence of Interleave Mode ............................................................................ 9
Auto-precharge Command .................................................................................................. 10
Precharge Command .......................................................................................................... 10
Self Refresh Command ....................................................................................................... 10
Power Down Mode .............................................................................................................. 11
No Operation Command...................................................................................................... 11
Deselect Command ............................................................................................................. 11
Clock Suspend Mode .......................................................................................................... 11
Simplified Stated Diagram................................................................................................... 13
Absolute Maximum Ratings................................................................................................. 14
Recommended DC Operating Conditions ........................................................................... 14
Capacitance......................................................................................................................... 15
DC Characteristics............................................................................................................... 15
Publication Release Date:Nov. 06, 2008
Revision A01
OPERATION MODE...................................................................................................................... 12
ELECTRICAL CHARACTERISTICS ............................................................................................. 14
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W9812G2IH
9.5
10
10.1
10.2
10.3
10.4
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
AC Characteristics and Operating Condition....................................................................... 16
Command Input Timing ....................................................................................................... 18
Read Timing ........................................................................................................................ 19
Control Timing of Input/Output Data.................................................................................... 20
Mode Register Set Cycle..................................................................................................... 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)............................................. 22
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge).................. 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)............................................. 24
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge).................. 25
Interleaved Bank Write (Burst Length = 8) .......................................................................... 26
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................... 27
Page Mode Read (Burst Length = 4, CAS Latency = 3) ..................................................... 28
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3).......................................... 29
Auto-precharge Read (Burst Length = 4, CAS Latency = 3)............................................... 30
TIMING WAVEFORMS.................................................................................................................. 18
Operating Timing Example ............................................................................................................ 22
11.10 Auto-precharge Write (Burst Length = 4) ............................................................................ 31
11.11 Auto Refresh Cycle.............................................................................................................. 32
11.12 Self Refresh Cycle............................................................................................................... 33
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3).................................... 34
11.14 Power Down Mode .............................................................................................................. 35
11.15 Auto-precharge Timing (Read Cycle).................................................................................. 36
11.16 Auto-precharge Timing (Write Cycle) .................................................................................. 37
11.17 Timing Chart of Read to Write Cycle................................................................................... 38
11.18 Timing Chart of Write to Read Cycle................................................................................... 38
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command) .................................................. 39
11.20 Timing Chart of Burst Stop Cycle (Precharge Command) .................................................. 39
11.21 CKE/DQM Input Timing (Write Cycle) ................................................................................. 40
11.22 CKE/DQM Input Timing (Read Cycle)................................................................................. 41
12
13
Package Specification ................................................................................................................... 42
12.1
86L TSOP (II)-400 mil.......................................................................................................... 42
REVISION HISTORY..................................................................................................................... 43
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Publication Release Date:Nov. 06, 2008
Revision A01
W9812G2IH
1
GENERAL DESCRIPTION
W9812G2IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1,048,576 words
×
4 banks
×
32 bits. W9812G2IH delivers a data bandwidth of up to 166M words per
second (-6). For different application, W9812G2IH is sorted into following speed grades: -6C, -6, -6I
and -75. The -6C/-6/-6I is compliant to the 166MHz/CL3 specification. (The speed grade of -6C
supports t
RP
=16nS, t
RCD
=16nS, t
RC
=48nS, t
AC
=4.5nS, t
IH
=0.8nS and the -6I speed grade which is
guaranteed to support -40°C ~ 85°C.) The -75 is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9812G2IH is ideal for main memory in
high performance applications.
2
•
•
•
•
•
•
•
•
•
•
•
•
FEATURES
3.3V ± 0.3V Power Supply
Up to 166 MHz Clock Frequency
1,048,576 Words
×
4 banks
×
32 bits organization
Self Refresh Mode
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM0-3
Auto-precharge and Controlled Precharge
4K Refresh cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 86-pin, using Lead free materials with RoHS compliant
3
AVAILABLE PART NUMBER
PART NUMBER
SPEED
MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
W9812G2IH-6C
W9812G2IH-6
W9812G2IH-6I
W9812G2IH-75
166MHz/CL3
166MHz/CL3
166MHz/CL3
133MHz/CL3
2mA
2mA
2mA
2mA
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
0°C ~ 70°C
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Publication Release Date:Nov. 06, 2008
Revision A01
W9812G2IH
4
PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDD
DQM0
WE#
CAS#
RAS#
CS#
A11
BS0
BS1
A10
A0
A1
A2
DQM2
VDD
NC
DQ16
VSSQ
DQ17
DQ18
VDDQ
DQ19
DQ20
VSSQ
DQ21
DQ22
VDDQ
DQ23
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSS
DQM1
NC
NC
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
NC
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS
-4-
Publication Release Date:Nov. 06, 2008
Revision A01
W9812G2IH
5
PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address. Row
address: A0−A11. Column address: A0−A7. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
25-27, 60-66, 24,21
A0−A11
Address
22,23
2,4,5,7,8,10,11,13,74,
76,77,79,80,82,83,85,
31,33,34,36,37,39,40,
42,45,47,48,50,51,53,
54,56
20
BS0, BS1
Bank Select
DQ0−DQ31
Data Input/
Output
Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and
previous operation continues.
19
RAS
CAS
WE
DQM0~3
Command input. When sampled at the rising edge of the
Row
Address
clock,
RAS
,
CAS
and
WE
define the operation to be
Strobe
executed.
Column
Address Strobe Referred to
RAS
Write Enable
Input/output
mask
Clock Inputs
Clock Enable
Power (+3.3V)
Ground
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
sampling DQM high will block the write operation with zero
latency.
System clock used to sample inputs on the rising edge of
clock.
CKE controls the clock activation and deactivation. When
CKE is low, Power Down mode, Suspend mode, or Self
Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
18
17
16,71,28,59
68
67
1,15,29,43
44,58,72,86
3,9,35,41,49,55,75,81
6,12,32,38,46,52,78,
84
14,30,57,69,70,73
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
Power (+3.3V) Separated power from VDD, to improve DQ noise
for I/O buffer
immunity.
Ground for I/O Separated ground from VSS, to improve DQ noise
buffer
immunity.
No Connection No connection
-5-
Publication Release Date:Nov. 06, 2008
Revision A01
