W981216DH / W9812G6DH
2M
×
4 BANKS
×
16 BIT SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
PIN CONFIGURATION ............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ............................................................................................. 7
RECOMMENDED DC OPERATING CONDITIONS................................................................... 7
CAPACITANCE........................................................................................................................... 7
AC CHARACTERISTICS AND OPERATING CONDITION........................................................ 8
DC CHARACTERISTICS ............................................................................................................ 9
OPERATION MODE ................................................................................................................. 12
FUNCTIONAL DESCRIPTION.................................................................................................. 13
12.1
12.2
12.3
12.4
12.5
12.6
12.7
12.8
12.9
12.10
12.11
12.12
12.13
12.14
12.15
12.16
12.17
12.18
12.19
12.20
Power Up and Initialization ........................................................................................... 13
Programming Mode Register........................................................................................ 13
Bank Activate Command .............................................................................................. 13
Read and Write Access Modes .................................................................................... 14
Burst Read Command .................................................................................................. 14
Burst Write Command .................................................................................................. 14
Read Interrupted by a Read ......................................................................................... 14
Read Interrupted by a Write.......................................................................................... 14
Write Interrupted by a Write.......................................................................................... 14
Write Interrupted by a Read ........................................................................................ 15
Burst Stop Command .................................................................................................. 15
Addressing Sequence of Sequential Mode ................................................................. 15
Addressing Sequence of Interleave Mode .................................................................. 16
Auto-Precharge Command.......................................................................................... 16
Precharge Command .................................................................................................. 16
Self Refresh Command ............................................................................................... 17
Power Down Mode ...................................................................................................... 17
No Operation Command ............................................................................................. 17
Deselect Command..................................................................................................... 17
Clock Suspend Mode .................................................................................................. 17
Publication Release Date: June 6, 2005
Revision A08
-1-
W981216DH / W9812G6DH
13.
TIMING WAVEFORMS ............................................................................................................. 18
13.1
13.2
13.3
13.4
14.
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
14.9
14.10
14.11
14.12
14.13
14.14
14.15
14.16
14.17
14.18
14.19
14.20
14.21
14.22
14.23
15.
16.
15.1
Command Input Timing ................................................................................................ 18
Read Timing.................................................................................................................. 19
Control Timing of Input/Output Data ............................................................................. 20
Mode Register Set Cycle .............................................................................................. 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge) ............ 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge) ............ 25
Interleaved Bank Write (Burst Length = 8) ................................................................... 26
Interleaved Bank Write (Burst Length = 8, Autoprecharge).......................................... 27
Page Mode Read (Burst Length = 4, CAS Latency = 3)............................................... 28
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ................................... 29
Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30
Auto Precharge Write (Burst Length = 4) .................................................................... 31
Auto Refresh Cycle ..................................................................................................... 32
Self Refresh Cycle....................................................................................................... 33
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)............................ 34
PowerDown Mode ....................................................................................................... 35
Autoprecharge Timing (Read Cycle)........................................................................... 36
Autoprecharge Timing (Write Cycle) ........................................................................... 37
Timing Chart of Read to Write Cycle........................................................................... 38
Timing Chart of Write to Read Cycle........................................................................... 38
Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39
Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
CKE/DQM Input Timing (Write Cycle)......................................................................... 40
CKE/DQM Input Timing (Read Cycle)......................................................................... 41
Self Refresh/Power Down Mode Exit Timing .............................................................. 42
54L TSOP (II)-400 mil................................................................................................... 43
OPERATING TIMING EXAMPLE ............................................................................................. 22
PACKAGE DIMENSION ........................................................................................................... 43
REVISION HISTORY ................................................................................................................ 44
-2-
W981216DH/ W9812G6DH
1. GENERAL DESCRIPTION
W981216DH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.13
µm
process technology,
W981216DH delivers a data bandwidth of up to 166M words per second (-6). For different application,
W981216DH is sorted into four speed grades: -6, -7, -75, and -8H. The –6 is compliant to the
166Mhz/CL3 specification, the -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -
75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981216DH is ideal for main memory in
high performance applications.
2. FEATURES
3.3V
±
0.3V Power Supply
Up to 166 MHz Clock Frequency
2,097,152 Words
×
4 banks
×
16 bits organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Auto-precharge and Controlled Precharge
4K Refresh cycles / 64 mS
Interface: LVTTL
Packaged in TSOP II 54 pin, 400 mil - 0.80
W9812G6DH is using Lead free materials, RoHS compliant
AVAILABLE PART NUMBER
PART NUMBER
SPEED
MAXIMUM SELF REFRESH
CURRENT
OPERATING
TEMPERATURE
W981216DH-6
W981216DH-7
W981216DH-75
W981216DH-8H
166MHz/CL3
PC133/CL2
PC133/CL3
PC100/CL2
3 mA
3 mA
3mA
3 mA
0°C - 70°C
0°C - 70°C
0°C - 70°C
0°C - 70°C
-3-
Publication Release Date: June 6, 2005
Revision A08
W981216DH / W9812G6DH
3. PIN CONFIGURATION
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
CC
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
CC
Q
DQ8
V
SS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
-4-
W981216DH/ W9812G6DH
4. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
23
−
26, 22,
29
−
35
20, 21
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
19
A0
−
A11
BS0, BS1
Address
Bank Select
Multiplexed pins for row and column address.
Row address: A0
−
A11. Column address: A0
−
A8.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
DQ0
−
DQ15
CS
Data Input/
Output
Chip Select
Row Address
Strobe
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the operation
to be executed.
18
17
16
39, 15
RAS
CAS
WE
Column Address
Referred to
RAS
Strobe
Write Enable
Input/Output
Mask
Clock Inputs
Clock Enable
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
Ground for input buffers and logic circuit inside DRAM.
UDQM/
LDQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Power (+3.3V) Separated power from V
CC
, used for output buffers to
for I/O Buffer improve noise.
Ground for I/O Separated ground from V
SS
, used for output buffers to
Buffer
improve noise.
No Connection No connection
-5-
Publication Release Date: June 6, 2005
Revision A08
