W9812G6IH
2M
×
4 BANKS
×
16 BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION .............................................................................................................. 3
FEATURES...................................................................................................................................... 3
AVAILABLE PART NUMBER .......................................................................................................... 3
PIN CONFIGURATION.................................................................................................................... 4
PIN DESCRIPTION ......................................................................................................................... 5
BLOCK DIAGRAM........................................................................................................................... 6
FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.
9.
Power Up and Initialization ................................................................................................. 7
Programming Mode Register .............................................................................................. 7
Bank Activate Command .................................................................................................... 7
Read and Write Access Modes .......................................................................................... 7
Burst Read Command ........................................................................................................ 8
Burst Write Command......................................................................................................... 8
Read Interrupted by a Read ............................................................................................... 8
Read Interrupted by a Write................................................................................................ 8
Write Interrupted by a Write ................................................................................................ 8
Write Interrupted by a Read................................................................................................ 8
Burst Stop Command.......................................................................................................... 9
Addressing Sequence of Sequential Mode......................................................................... 9
Addressing Sequence of Interleave Mode.......................................................................... 9
Auto-precharge Command................................................................................................ 10
Precharge Command........................................................................................................ 10
Self Refresh Command..................................................................................................... 10
Power Down Mode............................................................................................................ 11
No Operation Command ................................................................................................... 11
Deselect Command .......................................................................................................... 11
Clock Suspend Mode........................................................................................................ 11
OPERATION MODE...................................................................................................................... 12
ELECTRICAL CHARACTERISTICS ............................................................................................. 13
9.1
9.2
Absolute Maximum Ratings .............................................................................................. 13
Recommended DC Operating Conditions ........................................................................ 13
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Publication Release Date: Mar. 22, 2010
Revision A10
W9812G6IH
9.3
9.4
9.5
10.1
10.2
10.3
10.4
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
12.1
Capacitance ...................................................................................................................... 13
DC Characteristics ............................................................................................................ 14
AC Characteristics and Operating Condition .................................................................... 15
Command Input Timing..................................................................................................... 17
Read Timing...................................................................................................................... 18
Control Timing of Input/Output Data ................................................................................. 19
Mode Register Set Cycle .................................................................................................. 20
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) .......................................... 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............... 22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .......................................... 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............... 24
Interleaved Bank Write (Burst Length = 8) ....................................................................... 25
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26
Page Mode Read (Burst Length = 4, CAS Latency = 3)................................................... 27
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28
Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ............................................ 29
Auto Precharge Write (Burst Length = 4) ......................................................................... 30
Auto Refresh Cycle ........................................................................................................... 31
Self Refresh Cycle ............................................................................................................ 32
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ................................. 33
Power Down Mode............................................................................................................ 34
Auto-precharge Timing (Read Cycle) ............................................................................... 35
Auto-precharge Timing (Write Cycle) ............................................................................... 36
Timing Chart of Read to Write Cycle ................................................................................ 37
Timing Chart of Write to Read Cycle ................................................................................ 37
Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38
Timing Chart of Burst Stop Cycle (Precharge Command)................................................ 38
CKE/DQM Input Timing (Write Cycle) .............................................................................. 39
CKE/DQM Input Timing (Read Cycle) .............................................................................. 40
54L TSOP (II)-400 mil ....................................................................................................... 41
10. TIMING WAVEFORMS.................................................................................................................. 17
11. OPERATING TIMING EXAMPLE.................................................................................................. 21
12. PACKAGE SPECIFICATION......................................................................................................... 41
13. REVISION HISTORY..................................................................................................................... 42
-2-
Publication Release Date: Mar. 22, 2010
Revision A10
W9812G6IH
1. GENERAL DESCRIPTION
W9812G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2M words
×
4 banks
×
16 bits. W9812G6IH delivers a data bandwidth of up to 200M words per second
(-5). For different application, W9812G6IH is sorted into the following speed grades: -5/-6/-6C/-6I/-6A
and -75. The –5 is compliant to the 200MHz/CL3 specification. The -6/-6C/-6I/-6A is compliant to the
166MHz/CL3 specification (the -6I industrial grade, -6A automotive grade which is guaranteed to
support -40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9812G6IH is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
3.3V
±
0.3V Power Supply
Up to 200 MHz Clock Frequency
2,097,152 Words
×
4 banks
×
16 bits organization
Self Refresh Mode
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and full page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Auto-precharge and Controlled Precharge
4K Refresh cycles / 64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED
MAXIMUM SELF
REFRESH CURRENT
OPERATING
TEMPERATURE
W9812G6IH-5
W9812G6IH-6
W9812G6IH-6C
W9812G6IH-6I
W9812G6IH-6A
W9812G6IH-75
200MHz/CL3
166MHz/CL3
166MHz/CL3
166MHz/CL3
166MHz/CL3
133MHz/CL3
2 mA
2 mA
2 mA
2 mA
2 mA
2 mA
0°C ~ 70°C
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
-40°C ~ 85°C
0°C ~ 70°C
-3-
Publication Release Date: Mar. 22, 2010
Revision A10
W9812G6IH
4. PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
-4-
Publication Release Date: Mar. 22, 2010
Revision A10
W9812G6IH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
23
−
26, 22,
29
−
35
20, 21
2, 4, 5, 7, 8,
10, 11, 13, 42,
44, 45, 47, 48,
50, 51, 53
19
A0
−
A11
BS0, BS1
DQ0
−
DQ15
Address
Bank Select
Data Input/
Output
Multiplexed pins for row and column address.
Row address: A0
−
A11. Column address: A0
−
A8.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the
operation to be executed.
CS
Chip Select
Row Address
Strobe
18
17
16
39, 15
RAS
CAS
WE
Column Address
Referred to
RAS
Strobe
Write Enable
Input/Output
Mask
Clock Inputs
Clock Enable
Power (+3.3V)
Ground
Power (+3.3V)
for I/O Buffer
Ground for I/O
Buffer
No Connection
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising edge
of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend mode
or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
DD
, used for output buffers to
improve noise.
Separated ground from V
SS
, used for output buffers to
improve noise.
No connection
UDQM/
LDQM
CLK
CKE
V
DD
V
SS
V
DDQ
V
SSQ
NC
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
-5-
Publication Release Date: Mar. 22, 2010
Revision A10
