W9816G6BB
512K
×
2 BANKS
×
16 BITS SDRAM
Table of Contens-
1. GENERAL DESCRIPTION.................................................................................................................. 3
2. FEATURES ......................................................................................................................................... 3
3. PART NUMBER INFORMATION ........................................................................................................ 3
4. BALL CONFIGURATION .................................................................................................................... 4
5. BALL DESCRIPTION .......................................................................................................................... 5
6. BLOCK DIAGRAM .............................................................................................................................. 6
7. FUNCTIONAL DESCRIPTION............................................................................................................ 7
Power Up and Initialization................................................................................................................ 7
Programming Mode Register ............................................................................................................ 7
Bank Activate Command................................................................................................................... 7
Read and Write Access Modes......................................................................................................... 7
Burst Read Command....................................................................................................................... 8
Burst Write Command ....................................................................................................................... 8
Read Interrupted by a Read.............................................................................................................. 8
Read Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Write .............................................................................................................. 8
Write Interrupted by a Read .............................................................................................................. 8
Burst Stop Command ........................................................................................................................ 8
Addressing Sequence of Sequential Mode....................................................................................... 9
Addressing Sequence of Interleave Mode ........................................................................................ 9
Auto Precharge Command.............................................................................................................. 10
Precharge Command ...................................................................................................................... 10
Self Refresh Command................................................................................................................... 10
Power Down Mode .......................................................................................................................... 10
No Operation Command ................................................................................................................. 11
Deselect Command......................................................................................................................... 11
Clock Suspend Mode ...................................................................................................................... 11
Table of Operating Modes............................................................................................................... 12
8. ABSOLUTE MAXIMUM RATINGS.................................................................................................... 13
9. RECOMMENDED DC OPERATING CONDITIONS ......................................................................... 13
10. CAPACITANCE ............................................................................................................................... 13
-1-
Publication Release Date: January 2, 2003
Revision A1
W9816G6BB
11. DC CHARACTERISTICS ................................................................................................................ 14
12. AC CHARACTERISTICS ................................................................................................................ 15
13. TIMING WAVEFORMS ................................................................................................................... 17
Command Input Timing ................................................................................................................... 17
Read Timing .................................................................................................................................... 18
Control Timing of Input/Output Data ............................................................................................... 19
Mode Reqister Set Cycle ................................................................................................................ 20
Interleaved Bank Read.................................................................................................................... 21
Interleaved Bank Read.................................................................................................................... 22
Interleaved Bank Read.................................................................................................................... 23
Interleaved Bank Read.................................................................................................................... 24
Interleaved Bank Write .................................................................................................................... 25
Interleaved Bank Write .................................................................................................................... 26
Page Mode Read ............................................................................................................................ 27
Page Mode Read/Write................................................................................................................... 28
Auto Precharge Read...................................................................................................................... 29
Auto Precharge Write ...................................................................................................................... 30
Auto Refresh Cycle ......................................................................................................................... 31
Self Refresh Cycle........................................................................................................................... 32
Bust Read and Single Write ............................................................................................................ 33
Power Down Mode .......................................................................................................................... 34
Auto Precharge Timing ................................................................................................................... 35
Auto Precharge Timing ................................................................................................................... 36
Timing Chart of Write-to-Read Cycle .............................................................................................. 37
Timing Chart of Burst Stop Cycle.................................................................................................... 37
Timing Chart of Burst Stop Cycle (Prechare Command)................................................................ 38
CKE/DQM Input Timing................................................................................................................... 39
CKE/DQM Input Timing................................................................................................................... 40
Self Refresh/ Power Down Mode Exit Timing ................................................................................. 41
14. PACKAGE DIMENSIONS ............................................................................................................... 42
BGA 60 Balls Pitch = 0.65 mm........................................................................................................ 42
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W9816G6BB
1. GENERAL DESCRIPTION
W9816G6BB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words x 2 banks x 16 bits. Using pipelined architecture and 0.175
µm
process technology,
W9816G6BB delivers a data bandwidth of up to 286M bytes per second (-7).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6BB is ideal for main memory in
high performance applications.
2. FEATURES
•
2.7V
−
3.6V power supply
•
Up to 200 MHz clock frequency
•
524,288 words x 2 banks x 16 bits organization
•
Self Refresh Current: standard and low power
•
CAS latency: 2 and 3
•
Burst length: 1, 2, 4, 8, and full page
•
Burst read, single write mode
•
Byte data controlled by UDQM and LDQM
•
Auto-precharge and controlled precharge
•
4K refresh cycles/64 mS
•
Interface: LVTTL
•
Package: BGA 60 balls pitch = 0.65 mm using
PB free materials
3. PART NUMBER INFORMATION
PART NUMBER
W9816G6BB-7
SPEED (CL = 3)
143 MHz
SELF REFRESH CURRENT(MAX.)
1 mA
-3-
Publication Release Date: January 2, 2003
Revision A1
W9816G6BB
4. BALL CONFIGURATION
Top View
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Vss
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
BA
A8
A6
Vss
DQ15
VssQ
VDDQ
DQ11
VssQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
DQ0
VDDQ
VssQ
DQ4
VDDQ
VssQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
A3
Bottom View
6 7
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
VDD
7 6
DQ0
VDDQ
VssQ
DQ4
VDDQ
VssQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
A3
DQ15
VssQ
VDDQ
DQ11
VssQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
2 1
Vss
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
BA
A8
A6
Vss
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
-4-
W9816G6BB
5. BALL DESCRIPTION
BALL-LOCATION
BALL
NAME
FUNCTION
DESCRIPTION
N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7
M1
A6, B7, C7, D7, D6,
E7, F7, G7, G1, F1,
E1, D2, D1, C1, B1,
A2,
L7
A0
−
A10
Address
Bank
Address
Data Input/
Output
Multiplexed pins for row and column address.
Row address: A0
−
A10. Column address: A0
−
A7.
Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.
Multiplexed pins for data input and output.
BA
DQ0
−
DQ15
CS
K6
RAS
Disable or enable the command decoder. When
Chip Select command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
Row Address
the clock,
RAS
,
CAS
and
WE
define the
Strobe
operation to be executed.
Column
Address
Strobe
Referred to
RAS
K7
J7
J2/J6
CAS
WE
UDQM/
LDQM
CLK
CKE
V
DD
V
SS
V
DDQ
V
SSQ
NC
K2
L1
A7, R7
A1, R1
B6, C2, E6, F2
B2, C6, E2, F6
G2, G6, H1, H2, H6,
H7, J1, K1, L2, L6,
M6, M7
Write Enable Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
Input/Output when DQM is sampled high in read cycle. In write
Mask
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
Clock Inputs
edge of clock.
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power
Power for input buffers and logic circuit inside
(+3.3V)
DRAM.
Ground for input buffers and logic circuit inside
Ground
DRAM.
Power
Separated power from V
DD
, used for output buffers
(+3.3V) for
to improve noise immunity.
I/O buffer
Ground for Separated ground from V
SS
, used for output buffers
I/O buffer to improve noise immunity.
No
Connection
No connection
-5-
Publication Release Date: January 2, 2003
Revision A1
