W9816G6IB
512K
×
2 BANKS
×
16 BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
AVAILABLE PART NUMBER ..................................................................................................... 3
BALL CONFIGURATION ............................................................................................................ 4
BALL DESCRIPTION.................................................................................................................. 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.
9.
Power Up and Initialization ............................................................................................. 7
Programming Mode Register.......................................................................................... 7
Bank Activate Command ................................................................................................ 7
Read and Write Access Modes ...................................................................................... 7
Burst Read Command .................................................................................................... 8
Burst Write Command .................................................................................................... 8
Read Interrupted by a Read ........................................................................................... 8
Read Interrupted by a Write............................................................................................ 8
Write Interrupted by a Write............................................................................................ 8
Write Interrupted by a Read............................................................................................ 8
Burst Stop Command ..................................................................................................... 9
Addressing Sequence of Sequential Mode .................................................................... 9
Addressing Sequence of Interleave Mode ..................................................................... 9
Auto-precharge Command ........................................................................................... 10
Precharge Command.................................................................................................... 10
Self Refresh Command ................................................................................................ 10
Power Down Mode ....................................................................................................... 11
No Operation Command............................................................................................... 11
Deselect Command ...................................................................................................... 11
Clock Suspend Mode.................................................................................................... 11
OPERATION MODE ................................................................................................................. 12
ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1
9.2
Absolute Maximum Ratings .......................................................................................... 13
Recommended DC Operating Conditions .................................................................... 13
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Publication Release Date: Dec. 24, 2009
Revision A01
W9816G6IB
9.3
9.4
9.5
10.
10.1
10.2
10.3
10.4
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
12.
13.
12.1
Capacitance .................................................................................................................. 13
DC Characteristics........................................................................................................ 14
AC Characteristics ........................................................................................................ 15
Command Input Timing ................................................................................................ 17
Read Timing.................................................................................................................. 18
Control Timing of Input/Output Data............................................................................. 19
Mode Register Set Cycle .............................................................................................. 20
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 24
Interleaved Bank Write (Burst Length = 8) ................................................................... 25
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26
Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 27
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)................................... 28
Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 29
Auto Precharge Write (Burst Length = 4).................................................................... 30
Auto Refresh Cycle ..................................................................................................... 31
Self Refresh Cycle....................................................................................................... 32
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ........................... 33
Power Down Mode ...................................................................................................... 34
Auto-precharge Timing (Read Cycle) ......................................................................... 35
Auto-precharge Timing (Write Cycle).......................................................................... 36
Timing Chart of Read to Write Cycle........................................................................... 37
Timing Chart of Write to Read Cycle........................................................................... 37
Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 38
Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 38
CKE/DQM Input Timing (Write Cycle)......................................................................... 39
CKE/DQM Input Timing (Read Cycle)......................................................................... 40
VFBGA 60 Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø=0.4mm).................................. 41
TIMING WAVEFORMS ............................................................................................................. 17
OPERATING TIMING EXAMPLE ............................................................................................. 21
PACKAGE SPECIFICATION .................................................................................................... 41
REVISION HISTORY ................................................................................................................ 42
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Publication Release Date: Dec. 24, 2009
Revision A01
W9816G6IB
1. GENERAL DESCRIPTION
W9816G6IB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
×
2 banks
×
16 bits. W9816G6IB delivers a data bandwidth of up to 166M words per
second (-6). For different applications the W9816G6IB is sorted into two speed grades: -6 and -7. The
-6 parts can run up to 166MHz/CL3. The -7 parts can run up to 143MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6IB is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
2.7V~3.6V power supply for -7 speed grade
3.3V
±
0.3V power supply for -6 speed grade
524,288 words x 2 banks x 16 bits organization
Self Refresh current: standard and low power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Auto-precharge and Controlled Precharge
4K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in VFBGA 60 balls pitch=0.65mm, using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED GRADE
SELF REFRESH CURRENT
(MAX.)
OPERATING
TEMPERATURE
W9816G6IB-6
W9816G6IB-7
166MHz/CL3
143MHz/CL3
2mA
2mA
0°C ~ 70°C
0°C ~ 70°C
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Publication Release Date: Dec. 24, 2009
Revision A01
W9816G6IB
4. BALL CONFIGURATION
Top View
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Vss
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
BA
A8
A6
Vss
DQ15
VssQ
VDDQ
DQ11
VssQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
DQ0
VDDQ
VssQ
DQ4
VDDQ
VssQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
A3
Bottom View
6 7
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ6
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
VDD
7 6
DQ0
VDDQ
VssQ
DQ4
VDDQ
VssQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
A3
DQ15
VssQ
VDDQ
DQ11
VssQ
VDDQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
A4
2 1
Vss
DQ14
DQ13
DQ12
DQ10
DQ9
DQ8
NC
NC
NC
CKE
BA
A8
A6
Vss
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
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Publication Release Date: Dec. 24, 2009
Revision A01
W9816G6IB
5. BALL DESCRIPTION
Ball-Location
N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7
M1
Ball Name
A0−A10
Function
Address
Description
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.
Multiplexed pins for data input and output.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the
operation to be executed.
BA
Bank Address
A6, B7, C7, D7,
D6, E7, F7, G7,
DQ0−DQ15
G1, F1, E1, D2,
D1, C1, B1, A2,
L7
CS
Data Input/
Output
Chip Select
Row Address
Strobe
K6
K7
J7
J2/J6
RAS
CAS
WE
Column Address
Referred to
RAS
Strobe
Write Enable
Input/Output
Mask
Clock Inputs
Clock Enable
Power (+3.3V)
Ground
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
UDQM/
LDQM
CLK
CKE
V
CC
V
SS
V
CCQ
V
SS
Q
K2
L1
A7, R7
A1, R1
B6, C2, E6, F2
B2, C6, E2, F6
G2, G6, H1, H2,
H6, H7, J1, K1,
L2, L6, M6, M7
Power (+3.3V) for Separated power from V
CC
, used for output buffers
I/O buffer
to improve noise immunity.
Ground for I/O
buffer
No Connection
Separated ground from V
SS
, used for output buffers
to improve noise immunity.
No connection. (NC pin should be connected to
GND
or floating)
NC
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Publication Release Date: Dec. 24, 2009
Revision A01
