W9816G6IH
512K
×
2 BANKS
×
16 BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
AVAILABLE PART NUMBER ..................................................................................................... 3
PIN CONFIGURATION ............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.
9.
Power Up and Initialization ............................................................................................. 7
Programming Mode Register.......................................................................................... 7
Bank Activate Command ................................................................................................ 7
Read and Write Access Modes ...................................................................................... 7
Burst Read Command .................................................................................................... 8
Burst Write Command .................................................................................................... 8
Read Interrupted by a Read ........................................................................................... 8
Read Interrupted by a Write............................................................................................ 8
Write Interrupted by a Write............................................................................................ 8
Write Interrupted by a Read............................................................................................ 8
Burst Stop Command ..................................................................................................... 9
Addressing Sequence of Sequential Mode .................................................................... 9
Addressing Sequence of Interleave Mode ..................................................................... 9
Auto-precharge Command ........................................................................................... 10
Precharge Command.................................................................................................... 10
Self Refresh Command ................................................................................................ 10
Power Down Mode ....................................................................................................... 11
No Operation Command............................................................................................... 11
Deselect Command ...................................................................................................... 11
Clock Suspend Mode.................................................................................................... 11
OPERATION MODE ................................................................................................................. 12
ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1
9.2
Absolute Maximum Ratings .......................................................................................... 13
Recommended DC Operating Conditions .................................................................... 13
-1-
Publication Release Date: Mar. 22, 2010
Revision A02
W9816G6IH
9.3
9.4
9.5
10.
10.1
10.2
10.3
10.4
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
12.
13.
12.1
Capacitance .................................................................................................................. 13
DC Characteristics........................................................................................................ 14
AC Characteristics ........................................................................................................ 15
Command Input Timing ................................................................................................ 17
Read Timing.................................................................................................................. 18
Control Timing of Input/Output Data............................................................................. 19
Mode Register Set Cycle .............................................................................................. 20
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 24
Interleaved Bank Write (Burst Length = 8) ................................................................... 25
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26
Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 27
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)................................... 28
Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 29
Auto Precharge Write (Burst Length = 4).................................................................... 30
Auto Refresh Cycle ..................................................................................................... 31
Self Refresh Cycle....................................................................................................... 32
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ........................... 33
Power Down Mode ...................................................................................................... 34
Auto-precharge Timing (Read Cycle) ......................................................................... 35
Auto-precharge Timing (Write Cycle).......................................................................... 36
Timing Chart of Read to Write Cycle........................................................................... 37
Timing Chart of Write to Read Cycle........................................................................... 37
Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 38
Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 38
CKE/DQM Input Timing (Write Cycle)......................................................................... 39
CKE/DQM Input Timing (Read Cycle)......................................................................... 40
50L-TSOP (II) 400 mill .................................................................................................. 41
TIMING WAVEFORMS ............................................................................................................. 17
OPERATING TIMING EXAMPLE ............................................................................................. 21
PACKAGE SPECIFICATION .................................................................................................... 41
REVISION HISTORY ................................................................................................................ 42
-2-
Publication Release Date: Mar. 22, 2010
Revision A02
W9816G6IH
1. GENERAL DESCRIPTION
W9816G6IH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words
×
2 banks
×
16 bits. W9816G6IH delivers a data bandwidth of up to 200M words per
second. For different application, W9816G6IH is sorted into the following speed grades: -5/-6/-6I/-6A/-
7 and -7I. The -5 parts can run up to 200MHz/CL3 or 143MHz/CL2. The -6/-6I/-6A parts can run up to
166MHz/CL3 (the -6I industrial grade, -6A automotive grade which is guaranteed to support -40°C ~
85°C). The -7/-7I parts can run up to 143MHz/CL3 (the -7I grade which is guaranteed to support -40°C
~ 85°C).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6IH is ideal for main memory in
high performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
3.3V
±
0.3V power supply for -5/-6/-6I/-6A speed grades
2.7V~3.6V power supply for -7/-7I speed grades
524,288 words x 2 banks x 16 bits organization
Self Refresh current: standard and low power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Auto-precharge and Controlled Precharge
4K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in 50-pin, 400 mil TSOP II, using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED GRADE
SELF REFRESH CURRENT
(MAX.)
OPERATING
TEMPERATURE
W9816G6IH-5
W9816G6IH-6
W9816G6IH-7
W9816G6IH-6I
W9816G6IH-6A
W9816G6IH-7I
200MHz/CL3 or
143MHz/CL2
166MHz/CL3
143MHz/CL3
166MHz/CL3
166MHz/CL3
143MHz/CL3
2mA
2mA
2mA
2mA
2mA
2mA
0°C ~ 70°C
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
-40°C ~ 85°C
-40°C ~ 85°C
Publication Release Date: Mar. 22, 2010
Revision A02
-3-
W9816G6IH
4. PIN CONFIGURATION
V
CC
DQ0
DQ1
V
SS
Q
DQ2
DQ3
V
CC
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
CC
Q
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SS
Q
DQ13
DQ12
V
CC
Q
DQ11
DQ10
V
SS
Q
DQ9
DQ8
V
CC
Q
NC
UDQM
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
V
SS
-4-
Publication Release Date: Mar. 22, 2010
Revision A02
W9816G6IH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
20−24,
27−32
19
A0−A10
BA
Address
Bank Select
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
Select bank to activate during row address latch time,
or bank to read/write during column address latch
time.
Multiplexed pins for data input and output.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
2, 3, 5, 6, 8, 9,
11, 12, 39, 40,
DQ0−DQ15
42, 43, 45, 46,
48, 49
18
CS
Data
Input/ Output
Chip Select
17
16
15
36, 14
RAS
Command input. When sampled at the rising edge of
Row Address
the clock,
RAS
,
CAS
and
WE
define the operation
Strobe
to be executed.
Column
Address Strobe Referred to
RAS
Write Enable
Input/Output
Mask
Clock Inputs
Clock Enable
Power
Ground
Power for I/O
buffer
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from V
CC
, used for output buffers to
improve noise immunity.
CAS
WE
UDQM/
LDQM
CLK
CKE
V
CC
V
SS
V
CCQ
V
SSQ
NC
35
34
1, 25
26, 50
7, 13, 38, 44,
4, 10, 41, 47
33, 37
Ground for I/O Separated ground from V
SS
, used for output buffers
to improve noise immunity.
buffer
No Connection No connection.
-5-
Publication Release Date: Mar. 22, 2010
Revision A02
