W982508BH
8M
×
4 BANKS
×
8 BIT SDRAM
GENERAL DESCRIPTION
W982508BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
8M words
×
4 banks
×
8 bits. Using pipelined architecture and 0.175
µm
process technology,
W982508BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W982508BH is sorted into two speed grades: -7 and -75. The -
7 is compliant to the 143 MHz/CL3 or PC133 / CL2 specification, the -75 is compliant to the
PC133/CL3 specification, for handheld device application, we also provide a low power option, the 75L
grade, with Self Refresh Current under 1mA, and an industrial temperature option, the grade of 75I,
which is guranteed to support -40°C – 85°C.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982508BH is ideal for main memory in
high performance applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V
±
0.3V Power Supply
Up to 143 MHz Clock Frequency
8,388,608 Words
×
4 banks
×
8 bits organization
Auto Refresh and Self Refresh
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Power-Down Mode
Auto-Precharge and Controlled Precharge
8K Refresh cycles / 64 mS
Interface: LVTTL
Packaged in TSOP II 54 pin, 400 mil - 0.80
AVAILABLE PART NUMBER
Part Number
W982508BH- 7
W982508BH-75
W982508BH75L
W982508BH75I
Speed Grade
PC133/CL2
PC133/CL3
PC133/CL3
PC133/CL3
Self Refresh Current (Max)
3mA
3mA
1mA
1mA
Operating Temperature
0°C – 70°C
0°C – 70°C
0°C – 70°C
-40°C – 85°C
-1-
Publication Release Date: November 2000
Revision A0
W982508BH
PIN CONFIGURATION
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ7
V
SS
Q
NC
DQ6
V
CC
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
CC
Q
NC
V
SS
NC
DQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
-2-
W982508BH
PIN DESCRIPTION
Pin Number
23
−
26,22,
29
−
36
20, 21
Pin
Name
Function
Address
Bank Select
Description
Multiplexed pins for row and column address.
Row address : A0
−
A12. Column address: A0
−
A9.
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
A0
−
A12
BS0, BS1
2,5,8,11,44,47,
Data Input/
DQ0
−
DQ7 Output
50,53
19
18
17
16
39
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
CS#
RAS#
CAS#
WE#
DQM
CLK
CKE
V
CC
V
SS
V
CCq
V
SSq
Chip Select
Row Address
Strobe
Column Address
Referred to RAS#
Strobe
Write Enable
Referred to RAS#
The output buffer is placed at Hi-Z(with latency of 2) when DQM
input/output mask is sampled high in read cycle. In write cycle, sampling DQM high
will block the write operation with zero latency.
Clock Inputs
Clock Enable
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is
low, Power Down mode, Suspend mode, or Self Refresh mode is
entered.
Power ( +3.3 V ) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power ( + 3.3 V )
Separated power from V
CC
, to improve DQ noise immunity.
for I/O buffer
Ground for I/O
buffer
No Connection
Separated ground from V
SS
, to improve DQ noise immunity.
No connection
4,7,10,13,15,4
NC
0,42,45,48,51
-3-
Publication Release Date: June 2001
Revision A0
W982508BH
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
RAS
CAS
DECODER
CONTROL
SIGNAL
GENERATOR
COMMAND
COLUMN DECODER
WE
ROW DECODER
ROW DECODER
COLUMN DECODER
A10
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A0
A9
A11
A12
BS0
BS1
ADDRESS
BUFFER
MODE
REGISTER
SENSE AMPLIFIER
SENSE AMPLIFIER
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ7
REFRESH
COUNTER
COLUMN
COUNTER
DQM
COLUMN DECODER
ROW DECODER
ROW DECODER
COLUMN DECODER
CELL ARRAY
BANK #2
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
NOTE:
The cell array configuration is 8192 * 1024 * 8.
-4-
W982508BH
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input, Output Voltage
Supply Voltage
Operating Temperature(-7/-75/75L)
Operating Temperature(75I)
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
SYMBOL
V
IN,
V
OUT
V
CC
, V
CCQ
T
OPR
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
RATING
-0.3
−
V
CC
+0.3
-0.3
−
4.6
0
−
70
-40
−
85
-55
−
150
260
1
50
UNIT
V
V
°C
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
1
Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C for -7/-75/75L, Ta=-40 to 85°C for 75I)
PARAMETER
Supply Voltage
Supply Voltage (for I/O Buffer)
Input High Voltage
Input Low Voltage
SYMBOL
V
CC
V
CCQ
V
IH
V
IL
MIN.
3.0
3.0
2.0
-0.3
TYP.
3.3
3.3
-
-
MAX.
3.6
3.6
V
CC
+0.3
0.8
UNIT
V
V
V
V
NOTES
2
2
2
2
Note 2: V
IH
(max) = V
CC
/ V
CC
Q+1.2V for pulse width < 5 nS
V
IL
(min) = V
SS
/ V
SS
Q-1.2V for pulse width < 5 nS
CAPACITANCE
(V
CC
= 3.3V, f = 1 MHz, T
A
= 25°C)
PARAMETER
Input Capacitance
(A0 to A12, BS0, BS1, CS , RAS , CAS ,
WE
, LDQM,
UDQM, CKE)
Input Capacitance (CLK)
Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested.
SYMBOL
C
I
MIN.
-
MAX.
3.8
UNIT
pf
C
CLK
C
IO
-
-
3.5
6.5
pf
pf
-5-
Publication Release Date: June 2001
Revision A0
