W982516CH
4M
×
4 BANKS
×
16 BIT SDRAM
GENERAL DESCRIPTION
W982516CH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
4M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.13
µm
process technology,
W982516CH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the
personal computer industrial standard, W982516CH is sorted into two speed grades: -7 and -75. The -
7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3
specification, for handheld device application, we also provide a low power option, the 75L grade, with
Self Refresh Current under 1mA., and an industrial temperature option, the grade of 75I, which is
guranteed to support -40°C – 85°C.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W982516CH is ideal for main memory in
high performance applications.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V
±
0.3V Power Supply
Up to 143 MHz Clock Frequency
4,194,304 Words
×
4 Banks
×
16 Bits Organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8, and Full Page
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Power-down Mode
Auto-precharge and Controlled Precharge
8K Refresh Cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil - 0.80
AVAILABLE PART NUMBER
Part Number
W982516CH- 7
W982516CH-75
W982516CH75L
W982516CH75I
Speed Grade
PC133/CL2
PC133/CL3
PC133/CL3
PC133/CL3
Self Refresh Current (Max)
3mA
3mA
1mA
1mA
Operating Temperature
0°C - 70°C
0°C - 70°C
0°C - 70°C
-40°C - 85°C
-1-
Publication Release Date: Mar 2003
Revision A1
W982516CH
PIN CONFIGURATION
V
CC
DQ0
V
C C
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
C C
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
LDQM
WE
CAS
RAS
CS
BS0
BS1
A 1 0 /AP
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
C C
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
C C
Q
DQ8
V
SS
NC
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
-2-
W982516CH
PIN DESCRIPTION
PIN NO.
23−26, 22,
29−36
20, 21
PIN NAME
A0−A12
BS0, BS1
FUNCTION
Address
Bank Select
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0−A12. Column address: A0−A8.
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
2, 4, 5, 7, 8, 10,
11, 13, 42, 44,
DQ0−DQ16
45, 47, 48, 50,
51, 53
19
CS
Data
Multiplexed pins for data output and input.
Input/Output
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Chip Select
18
RAS
Command input. When sampled at the rising edge of
Row Address
the clock, RAS , CAS and WE define the operation
Strobe
to be executed.
Column
Address
Strobe
Referred to RAS
17
16
CAS
WE
LDQM,
UDQM
Write Enable Referred to RAS
The output buffer is placed at Hi-Z(with latency of 2)
Input/Output when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write operation
Mask
with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge
of clock.
15, 39
38
CLK
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
40
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
CKE controls the clock activation and deactivation.
Clock Enable When CKE is low, Power Down mode, Suspend mode,
or Self Refresh mode is entered.
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power (+3.3V) Separated power from V
CC
, to improve DQ noise
for I/O Buffer immunity.
Ground
Separated ground from V
SS
, to improve DQ noise
for I/O Buffer immunity.
No Connection No connection
-3-
Publication Release Date: Mar 2003
Revision A1
W982516CH
BLOCK DIAGRAM
CLK
CLOCK
BUFFER
CKE
CS
CONTROL
SIGNAL
RAS
COMMAND
CAS
DECODER
GENERATOR
COLUMN DECODER
WE
COLUMN DECODER
ROW DECODER
ROW DECODER
CELL ARRAY
BANK #0
CELL ARRAY
BANK #1
A10
A0
ADDRESS
BUFFER
MODE
R E G IST E R
SENSE AMPLIFIER
SENSE AMPLIFIER
A9
A11
A12
BS0
BS1
DATA CONTROL
CIRCUIT
DQ
BUFFER
DQ0
DQ15
REFRESH
COUNTER
COLUMN
COUNTER
LDQM
UDQM
COLUMN DECODER
COLUMN DECODER
ROW DECODER
CELL ARRAY
BANK #2
ROW DECODER
CELL ARRAY
BANK #3
SENSE AMPLIFIER
SENSE AMPLIFIER
Note: The cell array configuration is 8192 * 512 * 16.
-4-
W982516CH
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Input, Output Voltage
Supply Voltage
Operating Temperature(-7/-75/75L)
Operating Temperature(75I)
Storage Temperature
Soldering Temperature (10s)
Power Dissipation
Short Circuit Output Current
SYMBOL
V
IN,
V
OUT
V
CC
, V
CCQ
T
OPR
T
OPR
T
STG
T
SOLDER
P
D
I
OUT
RATING
-0.3
−
V
CC
+ 0.3
-0.3
−
4.6
0
−
70
-40
−
85
-55
−
150
260
1
50
UNIT
V
V
°C
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
1
Note 1: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
RECOMMENDED DC OPERATING CONDITIONS
(Ta = 0 to 70°C for -7/-75/75L, Ta=-40 to 85°C for 75I)
PARAMETER
Supply Voltage
Supply Voltage (for I/O Buffer)
Input High Voltage
Input Low Voltage
SYMBOL
V
CC
V
CCQ
V
IH
V
IL
MIN.
3.0
3.0
2.0
-0.3
TYP.
3.3
3.3
-
-
MAX.
3.6
3.6
V
CC
+0.3
0.8
UNIT
V
V
V
V
NOTES
2
2
2
2
Note 2: V
IH
(max) = V
CC
/ V
CC
Q+1.2V for pulse width < 5 nS
V
IL
(min) = V
SS
/ V
SS
Q-1.2V for pulse width < 5 nS
CAPACITANCE
(V
CC
= 3.3V, f = 1 MHz, T
A
= 25°C)
PARAMETER
Input Capacitance
(A0 to A12, BS0, BS1, CS , RAS , CAS , WE , LDQM,
UDQM, CKE)
Input Capacitance (CLK)
Input/Output Capacitance
Note: These parameters are periodically sampled and not 100% tested.
SYMBOL
C
I
MIN.
-
MAX.
3.8
UNIT
pf
C
CLK
C
IO
-
-
3.5
6.5
pf
pf
-5-
Publication Release Date: Mar 2003
Revision A1
