W9825G2JB
2M
4 BANKS
32BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ............................................................................................................. 3
FEATURES .................................................................................................................................... 3
AVAILABLE PART NUMBER ......................................................................................................... 3
BALL CONFIGURATION ............................................................................................................... 4
BALL DESCRIPTIONS ................................................................................................................... 5
BLOCK DIAGRAM.......................................................................................................................... 6
FUNCTIONAL DESCRIPTION ....................................................................................................... 7
7.1
Power Up and Initialization .................................................................................................. 7
7.2
Programming Mode Register............................................................................................... 7
7.3
Bank Activate Command ..................................................................................................... 7
7.4
Read and Write Access Modes ........................................................................................... 7
7.5
Burst Read Command ......................................................................................................... 8
7.6
Burst Write Command ......................................................................................................... 8
7.7
Read Interrupted by a Read ................................................................................................ 8
7.8
Read Interrupted by a Write ................................................................................................ 8
7.9
Write Interrupted by a Write................................................................................................. 8
7.10 Write Interrupted by a Read ................................................................................................ 8
7.11 Burst Stop Command .......................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode ......................................................................... 9
7.13 Addressing Sequence of Interleave Mode .......................................................................... 9
7.14 Auto-precharge Command ................................................................................................ 10
7.15 Precharge Command ........................................................................................................ 10
7.16 Self Refresh Command ..................................................................................................... 10
7.17 Power-down Mode ............................................................................................................. 11
7.18 No Operation Command .................................................................................................... 11
7.19 Deselect Command ........................................................................................................... 11
7.20 Clock Suspend Mode ........................................................................................................ 11
OPERATION MODE..................................................................................................................... 12
ELECTRICAL CHARACTERISTICS ............................................................................................ 13
9.1
Absolute Maximum Ratings ............................................................................................... 13
9.2
Recommended DC Operating Conditions ......................................................................... 13
9.3
Capacitance ....................................................................................................................... 13
9.4
DC Characteristics ............................................................................................................. 14
9.5
AC Characteristics and Operating Condition ..................................................................... 15
TIMING WAVEFORMS ................................................................................................................ 17
10.1 Command Input Timing ..................................................................................................... 17
10.2 Read Timing ...................................................................................................................... 18
Publication Release Date: Apr. 11, 2011
Revision A01
8.
9.
10.
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W9825G2JB
10.3 Control Timing of Input/Output Data .................................................................................. 19
10.4 Mode Register Set Cycle ................................................................................................... 20
OPERATING TIMING EXAMPLE................................................................................................. 21
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) ........................................... 21
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ................ 22
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) ........................................... 23
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ................ 24
11.5 Interleaved Bank Write (Burst Length = 8) ........................................................................ 25
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................. 26
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................... 27
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ........................................ 28
11.9 Auto-precharge Read (Burst Length = 4, CAS Latency = 3) ............................................. 29
11.10 Auto-precharge Write (Burst Length = 4) .......................................................................... 30
11.11 Auto Refresh Cycle ............................................................................................................ 31
11.12 Self Refresh Cycle ............................................................................................................. 32
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) .................................. 33
11.14 Auto-precharge Timing (Read Cycle) ................................................................................ 34
11.15 Auto-precharge Timing (Write Cycle) ................................................................................ 35
11.16 Timing Chart of Read to Write Cycle ................................................................................. 36
11.17 Timing Chart of Write to Read Cycle ................................................................................. 36
11.18 Timing Chart of Burst Stop Cycle (Burst Stop Command) ................................................ 37
11.19 Timing Chart of Burst Stop Cycle (Precharge Command) ................................................ 37
11.20 CKE/DQM Input Timing (Write Cycle) ............................................................................... 38
11.21 CKE/DQM Input Timing (Read Cycle) ............................................................................... 39
PACKAGE SPECIFICATION ....................................................................................................... 40
REVISION HISTORY ................................................................................................................... 41
11.
12.
13.
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Publication Release Date: Apr. 11, 2011
Revision A01
W9825G2JB
1. GENERAL DESCRIPTION
W9825G2JB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
2,097,152 words
4 banks
32 bits. W9825G2JB delivers a data bandwidth of up to 166M words per
second. For different application, W9825G2JB is sorted into two speed grades: -6, -75. The -6/-6I is
compliant to the 166MHz/CL3 specification, (the -6I grade which is guaranteed to support -40°C ~
85°C) ,the -75/75I is compliant to the PC133/CL3 specification (the 75I grade which is guaranteed to
support -40°C ~ 85°C).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9825G2JB is ideal for main memory in
high performance applications.
2. FEATURES
3.3V
0.3V for -6 speed grades power supply
2.7V~3.6V for -6I/-75/75I speed grades power supply
Up to 166 MHz Clock Frequency
2,097,152 Words
4 banks
32 bits organization
Self Refresh Mode: Standard and Low Power
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and full page
Burst Read, Single Writes Mode
Byte Data Controlled by DQM
Auto-precharge and Controlled Precharge
4K Refresh cycles / 64 mS
Interface: LVTTL
Package: 90 Balls TFBGA, using Lead free materials with RoHS compliant
Dual-Die package
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED GRADE
SELF REFRESH
CURRENT (MAX)
OPERATING
TEMPERATURE
W9825G2JB-6
W9825G2JB-6I
W9825G2JB-75
W9825G2JB75I
166MHz/CL3
166MHz/CL3
133MHz/CL3
133MHz/CL3
4 mA
4 mA
4 mA
4 mA
0°C ~ 70°C
-40°C ~ 85°C
0°C ~ 70°C
-40°C ~ 85°C
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Publication Release Date: Apr. 11, 2011
Revision A01
W9825G2JB
4. BALL CONFIGURATION
Top View
1
A
DQ26
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
A8
CKE
NC
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
VSSQ
DQ25
DQ30
NC
A3
A6
NC
A9
NC
VSS
DQ9
DQ14
VSSQ
VSS
VDD
VDDQ
DQ22
DQ17
NC
A2
A10
NC
BS0
CAS#
VDD
DQ6
DQ1
VDDQ
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
BS1
CS#
WE#
DQ7
DQ5
DQ3
VSSQ
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A1
A11
RAS#
DQM0
VSSQ
VDDQ
VDDQ
DQ4
2
3
4
5
6
7
8
9
B
DQ28
C
VSSQ
D
VSSQ
E
VDDQ
F
VSS
G
A4
H
A7
J
CLK
K
DQM1
L
VDDQ
M
VSSQ
N
VSSQ
P
DQ11
R
DQ13
VDD
DQ0
DQ2
-4-
Publication Release Date: Apr. 11, 2011
Revision A01
W9825G2JB
5. BALL DESCRIPTIONS
BALL LOCATION PIN NAME
G8,G9,F7,F3,G1,G2,
G3,H1,H2,J3,G7,H9
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address. Row
address: A0A11. Column address: A0A8. A10 is
sampled during a precharge command to determine if all
banks are to be precharged or bank selected by BS0,
BS1.
Select bank to activate during row address latch time, or
bank to read/write during address latch time.
A0A11
Address
J7,H8
BS0, BS1
Bank Select
A1,A2,A8,A9,B1,B9,
C2,C3,C7,C8,D2,D3,
D7,D8,E2,E8,L2,L8,
DQ0DQ31
M2,M3,M7,M8,N2,N3
,N7,N8,P1,P9,R1,R2,
R8,R9
J8
Data Input/
Output
Multiplexed pins for data output and input.
CS
Chip Select
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and
previous operation continues.
Command input. When sampled at the rising edge of the
clock
RAS
,
CAS
and
WE
define the operation to be
executed.
J9
RAS
CAS
WE
DQM03
Row Address
Strobe
K7
K8
Column Address
Referred to
RAS
Strobe
Write Enable
Referred to
RAS
F2,F8,K1,K9
The output buffer is placed at Hi-Z (with latency of 2) when
DQM is sampled high in read cycle. In write cycle,
Input/output mask
sampling DQM high will block the write operation with zero
latency.
Clock Inputs
Clock Enable
Power
Ground
Power for I/O
buffer
Ground for I/O
buffer
No Connection
System clock used to sample inputs on the rising edge of
clock.
CKE controls the clock activation and deactivation. When
CKE is low, Power-down mode, Suspend mode, or Self
Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from V
DD
, to improve DQ noise
immunity.
Separated ground from V
SS
, to improve DQ noise
immunity.
No connection.
J1
J2
A7,F9,L7,R7
A3,F1,L3,R3
B2,B7,C9,D9,E1,L1,
M9,N9,P2,P7
B8,B3,C1,D1,E9,L9,
M1,N1,P3,P8,
E3,E7,H3,H7,K2,K3
CLK
CKE
VDD
VSS
VDDQ
VSSQ
NC
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Publication Release Date: Apr. 11, 2011
Revision A01
