W9864G6GH
1M
×
4 BANKS
×
16 BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES ................................................................................................................................. 3
AVAILABLE PART NUMBER ..................................................................................................... 4
PIN CONFIGURATION ............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 5
BLOCK DIAGRAM ...................................................................................................................... 6
FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.
9.
Power Up and Initialization ............................................................................................. 7
Programming Mode Register Set command .................................................................. 7
Bank Activate Command ................................................................................................ 7
Read and Write Access Modes ...................................................................................... 7
Burst Read Command .................................................................................................... 8
Burst Command.............................................................................................................. 8
Read Interrupted by a Read ........................................................................................... 8
Read Interrupted by a Write............................................................................................ 8
Write Interrupted by a Write............................................................................................ 8
Write Interrupted by a Read............................................................................................ 8
Burst Stop Command ..................................................................................................... 9
Addressing Sequence of Sequential Mode .................................................................... 9
Addressing Sequence of Interleave Mode ..................................................................... 9
Auto-precharge Command ........................................................................................... 10
Precharge Command.................................................................................................... 10
Self Refresh Command ................................................................................................ 10
Power Down Mode ....................................................................................................... 11
No Operation Command............................................................................................... 11
Deselect Command ...................................................................................................... 11
Clock Suspend Mode.................................................................................................... 11
OPERATION MODE ................................................................................................................. 12
ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1
9.2
Absolute Maximum Ratings .......................................................................................... 13
Recommended DC Operating Conditions .................................................................... 13
Publication Release Date:Aug. 13, 2007
Revision A09
-1-
W9864G6GH
9.3
9.4
9.5
10.
10.1
10.2
10.3
10.4
11.
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
12.
13.
12.1
Capacitance .................................................................................................................. 13
DC Characteristics........................................................................................................ 14
AC Characteristics and Operating Condition................................................................ 15
Command Input Timing ................................................................................................ 18
Read Timing.................................................................................................................. 19
Control Timing of Input/Output Data............................................................................. 20
Mode Register Set Cycle .............................................................................................. 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 22
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 24
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 25
Interleaved Bank Write (Burst Length = 8) ................................................................... 26
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 27
Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 28
Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) ..................................... 29
Auto-precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 30
Auto-precharge Write (Burst Length = 4) .................................................................... 31
Auto Refresh Cycle ..................................................................................................... 32
Self Refresh Cycle....................................................................................................... 33
Bust Read and Single Write (Burst Length = 4, CAS Latency = 3)............................. 34
Power-down Mode ...................................................................................................... 35
Auto-precharge Timing (Write Cycle).......................................................................... 36
Auto-precharge Timing (Read Cycle) ......................................................................... 37
Timing Chart of Read to Write Cycle........................................................................... 38
Timing Chart of Write to Read Cycle........................................................................... 38
Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 39
Timing Chart of Burst Stop Cycle (Precharge Command) .......................................... 39
CKE/DQM Input Timing (Write Cycle)......................................................................... 40
CKE/DQM Input Timing (Read Cycle)......................................................................... 41
54L TSOP (II)-400 mil................................................................................................... 42
TIMING WAVEFORMS ............................................................................................................. 18
OPERATINOPERATING TIMING EXAMPLE........................................................................... 22
PACKAGE SPECIFICATION .................................................................................................... 42
REVISION HISTORY ................................................................................................................ 43
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Publication Release Date:Aug. 13, 2007
Revision A09
W9864G6GH
1. GENERAL DESCRIPTION
W9864G6GH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words
×
4 banks
×
16 bits. Using pipelined architecture and 0.11 µm process technology,
W9864G6GH delivers a data bandwidth of up to 400M bytes per second. For different application,
W9864G6GH is sorted into the following speed grades: -5, -6/-6I, -7/-7S. The -5 parts can run up to
200MHz/CL3. The -6/-6I parts can run up to 166MHz/CL3. The -7/-7S parts can run up to
143MHz/CL3. And the grade of –7S with tRP=18nS.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time.By
having a programmable Mode Register, the system can change burst length, latency cycle, interleave
or sequential burst to maximize its performance. W9864G6GH is ideal for main memory in high
performance applications.
2. FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
3.3V± 0.3V for -5/-6/-6I grade power supply
2.7V
½
3.6V for -7/-7S grade power supply
1,048,576 words
×
4 banks
×
16 bits organization
Self Refresh Current: Standard and Low Power
CAS Latency: 2 & 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Byte data controlled by LDQM, UDQM
Auto-precharge and controlled precharge
Burst read, single write operation
4K refresh cycles/64 mS
Interface: LVTTL
Packaged in TSOP II 54-pin, 400 mil
W9864G6GH is using Lead free materials
-3-
Publication Release Date:Aug. 13, 2007
Revision A09
W9864G6GH
3. AVAILABLE PART NUMBER
PART NUMBER
SPEED (CL=3)
SELF REFRESH
CURRENT (MAX.)
OPERATING
TEMPERATURE
W9864G6GH-5
W9864G6GH-6
W9864G6GH-7/-7S
W9864G6GH-6I
200 MHz
166 MHz
143 MHz
166 MHz
2mA
2mA
2mA
2mA
0°C ~ 70°C
0°C ~ 70°C
0°C ~ 70°C
-40°C ~ 85°C
4. PIN CONFIGURATION
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
VDD
LDQM
WE
CAS
RAS
CS
BS0
BS1
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
VSS
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Publication Release Date:Aug. 13, 2007
Revision A09
W9864G6GH
5. PIN DESCRIPTION
PIN NUMBER
PIN NAME
FUNCTION
DESCRIPTION
Multiplexed pins for row and column address.
23 ~ 26, 22,
29 ~35
Row address: A0−A11. Column address: A0−A7.
A0−A11
Address
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch time,
or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock
RAS
,
CAS
and
WE
define the
operation to be executed.
Referred to
RAS
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside
DRAM.
for I/O
Separated power from VDD, to improve DQ noise
immunity.
Separated ground from V
SS
, to improve DQ noise
immunity.
No connection.(The NC pin must connect to
20, 21
BS0, BS1
Bank Select
2, 4, 5, 7, 8, 10,
Data
11, 13, 42, 44,
DQ0−DQ15
45, 47, 48, 50,
Input/ Output
51, 53
19
CS
Chip Select
18
RAS
Row Address
Strobe
Column
Address Strobe
Write Enable
Input/output
mask
17
16
CAS
WE
UDQM
LDQM
CLK
39, 15
38
Clock Inputs
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
36, 40
CKE
VDD
V
SS
VDDQ
VSSQ
NC
Clock Enable
Power
Ground
Power
buffer
Ground for I/O
buffer
No Connection
ground or floating.)
-5-
Publication Release Date:Aug. 13, 2007
Revision A09
