W9864G6JT
1M
4 BANKS
16 BITS SDRAM
Table of Contents-
1.
2.
3.
4.
5.
6.
7.
GENERAL DESCRIPTION .............................................................................................................. 3
FEATURES ...................................................................................................................................... 3
ORDER INFORMATION.................................................................................................................. 3
BALL CONFIGURATION ................................................................................................................. 4
BALL DESCRIPTION ...................................................................................................................... 5
BLOCK DIAGRAM ........................................................................................................................... 6
FUNCTIONAL DESCRIPTION ........................................................................................................ 7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
7.15
7.16
7.17
7.18
7.19
7.20
8.
9.
Power Up and Initialization ................................................................................................. 7
Programming Mode Register .............................................................................................. 7
Bank Activate Command .................................................................................................... 7
Read and Write Access Modes .......................................................................................... 7
Burst Read Command ........................................................................................................ 8
Burst Write Command......................................................................................................... 8
Read Interrupted by a Read................................................................................................ 8
Read Interrupted by a Write ................................................................................................ 8
Write Interrupted by a Write ................................................................................................ 8
Write Interrupted by a Read ................................................................................................ 8
Burst Stop Command.......................................................................................................... 9
Addressing Sequence of Sequential Mode......................................................................... 9
Addressing Sequence of Interleave Mode .......................................................................... 9
Auto-precharge Command................................................................................................ 10
Precharge Command ........................................................................................................ 10
Self Refresh Command..................................................................................................... 10
Power Down Mode ............................................................................................................ 11
No Operation Command ................................................................................................... 11
Deselect Command .......................................................................................................... 11
Clock Suspend Mode ........................................................................................................ 11
OPERATION MODE ...................................................................................................................... 12
ELECTRICAL CHARACTERISTICS ............................................................................................. 13
9.1
9.2
Absolute Maximum Ratings .............................................................................................. 13
Recommended DC Operating Conditions ........................................................................ 13
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Publication Release Date: Mar. 31, 2017
Revision: A03
W9864G6JT
9.3
9.4
9.5
10.1
10.2
10.3
10.4
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
11.17
11.18
11.19
11.20
11.21
11.22
Capacitance ...................................................................................................................... 13
DC Characteristics ............................................................................................................ 14
AC Characteristics and Operating Condition .................................................................... 15
Command Input Timing..................................................................................................... 17
Read Timing ...................................................................................................................... 18
Control Timing of Input/Output Data ................................................................................. 19
Mode Register Set Cycle .................................................................................................. 20
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) .......................................... 21
Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) ............... 22
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) .......................................... 23
Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) ............... 24
Interleaved Bank Write (Burst Length = 8) ....................................................................... 25
Interleaved Bank Write (Burst Length = 8, Auto-precharge) ............................................ 26
Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................... 27
Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) ....................................... 28
Auto Precharge Read (Burst Length = 4, CAS Latency = 3) ............................................ 29
Auto Precharge Write (Burst Length = 4) ......................................................................... 30
Auto Refresh Cycle ........................................................................................................... 31
Self Refresh Cycle ............................................................................................................ 32
Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ................................. 33
Power down Mode ............................................................................................................ 34
Auto-precharge Timing (Read Cycle) ............................................................................... 35
Auto-precharge Timing (Write Cycle) ............................................................................... 36
Timing Chart of Read to Write Cycle ................................................................................ 37
Timing Chart of Write to Read Cycle ................................................................................ 37
Timing Chart of Burst Stop Cycle (Burst Stop Command) ............................................... 38
Timing Chart of Burst Stop Cycle (Precharge Command) ................................................ 38
CKE/DQM Input Timing (Write Cycle) .............................................................................. 39
CKE/DQM Input Timing (Read Cycle) .............................................................................. 40
10. TIMING WAVEFORMS.................................................................................................................. 17
11. OPERATING TIMING EXAMPLE .................................................................................................. 21
12. PACKAGE SPECIFICATION ......................................................................................................... 41
13. REVISION HISTORY..................................................................................................................... 42
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Publication Release Date: Mar. 31, 2017
Revision: A03
W9864G6JT
1. GENERAL DESCRIPTION
W9864G6JT is a high-speed synchronous dynamic random access memory (SDRAM), organized as
1M words
4 banks
16 bits. W9864G6JT delivers a data bandwidth of up to 166M words per
second. W9864G6JT is sorted into too speed grades: -6 and -6I. They are compliant to the
166MHz/CL3 specification (-6I industrial grade which is guaranteed to support -40°C ≤ T
A
≤ 85°C).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle.
The multiple bank nature enables interleaving among internal banks to hide the precharging time. By
having a programmable Mode Register, the system can change burst length, latency cycle, interleave
or sequential burst to maximize its performance. W9864G6JT is ideal for main memory in high
performance applications.
2. FEATURES
3.3V ± 0.3V Power Supply
Up to 166 MHz Clock Frequency
1,048,576 Words
4 banks
16 bits organization
Self Refresh Mode
CAS Latency: 2 and 3
Burst Length: 1, 2, 4, 8 and full page
Sequential and Interleave Burst
Burst Read, Single Writes Mode
Byte Data Controlled by LDQM, UDQM
Power Down Mode
Auto-precharge and Controlled Precharge
4K Refresh cycles/64 mS
Interface: LVTTL
Packaged in TFBGA 54 Ball (8x8 mm
2
), using lead free materials with RoHS compliant
3. ORDER INFORMATION
PART NUMBER
SPEED
SELF REFRESH
CURRENT (MAX.)
OPERATING
TEMPERATURE
W9864G6JT-6
W9864G6JT-6I
166MHz/CL3
166MHz/CL3
2 mA
2 mA
0°C ~ 70°C
-40°C ~ 85°C
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Publication Release Date: Mar. 31, 2017
Revision: A03
W9864G6JT
4. BALL CONFIGURATION
Top View
1
2
3
4
5
6
7
8
9
A
VSS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
VSSQ
VDDQ
VSSQ
VDDQ
VSS
CKE
A9
A6
A4
VDDQ
VSSQ
VDDQ
VSSQ
VDD
/CAS
BS0
A0
A3
DQ0
DQ2
DQ4
DQ6
LDQM
/RAS
BS1
A1
A2
VDD
DQ1
DQ3
DQ5
DQ7
/WE
/CS
A10
VDD
B
DQ14
C
DQ12
D
DQ10
E
DQ8
F
UDQM
G
NC
H
A8
J
VSS
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Publication Release Date: Mar. 31, 2017
Revision: A03
W9864G6JT
5. BALL DESCRIPTION
BALL LOCATION BALL NAME
FUNCTION
DESCRIPTION
H7, H8, J8, J7, J3,
J2, H3, H2, H1,
G3, H9, G2
G7, G8
A0A11
Address
BS0, BS1
Bank Select
Data
Input/ Output
Multiplexed pins for row and column address.
Row address: A0A11. Column address: A0A7.
A10 is sampled during a precharge command to
determine if all banks are to be precharged or bank
selected by BS0, BS1.
Select bank to activate during row address latch
time, or bank to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock
RAS
,
CAS
and
WE
define the
operation to be executed.
A8, B9, B8, C9,
C8, D9, D8, E9,
E1, D2, D1, C2,
C1, B2, B1, A2
G9
DQ0DQ15
CS
Chip Select
Row Address
Strobe
F8
F7
F9
RAS
CAS
Column Address
Referred to
RAS
Strobe
Write Enable
Input/output
mask
Clock Inputs
Clock Enable
Power
Ground
Power for I/O
buffer
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside
DRAM.
Ground for input buffers and logic circuit inside
DRAM.
Separated power from V
DD
, to improve DQ noise
immunity.
WE
UDQM,
LDQM
CLK
CKE
V
DD
V
SS
V
DDQ
V
SSQ
NC
F1, E8
F2
F3
A9, E7, J9
A1, E3, J1
A7, B3, C7, D3
A3, B7, C3, D7
E2, G1
Ground for I/O Separated ground from V
SS
, to improve DQ noise
buffer
immunity.
No Connection No connection.
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Publication Release Date: Mar. 31, 2017
Revision: A03
