Latch-Up Current.................................................... >200 mA
Operating Range
Range
Industrial
Ambient Temperature
–40
°
C to +85
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
WCMS0808C1X
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Leakage
Current
V
CC
Operating Supply
Current
Automatic CE
Power-Down Current—
TTL Inputs
Automatic CE
Power-Down Current—
CMOS Inputs
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Dis-
abled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
,
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
−
0.3V
V
IN
> V
CC
−
0.3V
or V
IN
< 0.3V, f = 0
Test Conditions
V
CC
= Min., I
OH
=
−1.0
mA
V
CC
= Min., I
OL
= 2.1 mA
2.2
−0.5
−0.5
−0.5
25
Min.
2.4
0.4
V
CC
+0.5V
0.8
+0.5
+0.5
50
Typ
[2]
Max.
Unit
V
V
V
V
µA
µA
mA
I
SB1
0.3
0.5
mA
I
SB2
0.1
10
µA
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
6
8
Unit
pF
pF
Note:
1. V
IL
(min.) =
−
2.0V for pulse durations of less than 20 ns.
2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(T
A
= 25
°
C, V
CC
). Parameters are guaranteed by design and characterization, and not 100% tested.
3. Tested initially and after any design or process changes that may affect these parameters.
*
WCMS0808C1X
AC Test Loads and Waveforms
R1 1800
Ω
5V
OUTPUT
100 pF
INCLUDING
JIG AND
SCOPE
R2
990
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
990
Ω
3.0V
10%
GND
< 5 ns
R1 1800
Ω
ALL INPUT PULSES
90%
90%
10%
< 5 ns
(a)
Equivalent to:
THÉ
VENIN EQUIVALENT
639
Ω
OUTPUT
1.77V
(b)
Data Retention Characteristics
Parameter
V
DR
Description
V
CC
for Data Retention
Conditions
[4]
V
CC
= 3.0V,
CE > V
CC
−
0.3V,
V
IN
> V
CC
−
0.3V or
V
IN
< 0.3V
Min.
2.0
Typ.
[2]
Max.
Unit
V
I
CCDR
t
CDR[3]
t
R[3]
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery
Time
0
t
RC
0.1
10
µA
ns
ns
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
> 2V
3.0V
t
R
Note:
4. No input may exceed V
CC
+0.5V.
*
WCMS0808C1X
Switching Characteristics
Over the Operating Range
[10]
WCMS0808C1X
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
[8, 9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[6, 7]
WE HIGH to Low Z
[6]
5
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[6]
OE HIGH to High Z
[6, 7]
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
0
70
5
25
5
25
5
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the
specified I
OL
/I
OH
and 100-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
9. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
*
WCMS0808C1X
Switching Waveforms
Read Cycle No. 1
[10,11]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
Read Cycle No. 2
[11,12]
CE
t
ACE
OE
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
RC
t
HZOE
t
HZCE
DATA VALID
t
PD
HIGH
IMPEDANCE
DATA OUT
ICC
50%
ISB
Notes:
10. Device is continuously selected. OE, CE = V
IL
.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
