Available with 1.5ns setup and 0.5ns hold times or
1.0ns setup and hold times.
Single +3.3V power supply (V
CC
)
Seperate +3.3V or +2.5V isolated output buffer
supply (V
CCQ
)
Snooze Mode for reduced-power standby
Single-cycle deselect
Common data inputs and data outputs
Individual Byte Write control and Global Write
Clock-controlled and registered addresses, data
I/Os and control signals
Burst control (interleaved or linear burst)
Packaging:
•
119-bump BGA package
Low capacitive bus loading
IEEE 1149.1 JTAG Compatible Boundary Scan
WED2DL36513V
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC’s 16Mb SyncBurst
SRAMs integrate two 512K x 18 SRAMs into a single BGA
package to provide 512K x 36 configuration. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single-clock input (CK). The synchronous
inputs include all addresses, all data inputs, active LOW
chip enable (CS#), burst control inputs (ADSC#, ADSP#,
ADV#), byte write enables (BW#0-3) and global write
(GW#). Asynchronous inputs include the output enable
(OE#), clock (CK) and snooze enable (ZZ). There is also a
burst mode input (MODE) that selects between interleaved
and linear burst modes. Write Cycles can be from one to
four bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status
processor (ADSP#) or address status controller (ADSC#)
inputs. Subsequent burst addresses can be internally
generated as controlled by the burst advance input
(ADV#).
* This is subject to change without notice.
PIN CONFIGURATION
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
V
CCQ
NC
NC
DQc
DQc
V
CCQ
DQc
DQc
V
CCQ
DQd
DQd
V
CCQ
DQd
DQd
NC
NC
V
CCQ
2
SA
SA
SA
DQPc
DQc
DQc
DQc
DQc
V
CC
DQd
DQd
DQd
DQd
DQPd
SA
NC
TMD
3
SA
SA
SA
V
SS
V
SS
V
SS
BWc#
V
SS
NC
V
SS
BWd#
V
SS
V
SS
V
SS
MODE
SA
TDI
4
ADSP#
ADSC#
V
CC
NC
CS#
OE#
ADV#
GW#
V
CC
CK
NC
BWE#
SA1
SA0
V
CC
SA
TCK
5
SA
SA
SA
V
SS
V
SS
V
ss
BWb#
V
SS
NC
V
SS
BWa#
V
SS
V
SS
V
SS
NC
SA
TDO
6
SA
SA
SA
DQPb
DQb
DQb
DQb
DQb
V
CC
DQa
DQa
DQa
DQa
DQPa
SA
NC
NC
7
V
CCQ
NC
NC
DQb
DQb
V
CCQ
DQb
DQb
V
CCQ
DQa
DQa
V
CCQ
DQa
DQa
NC
ZZ
V
CCQ
BW
a#
BW
d#
GW#
ADV#
SA
CK
ADSP#
ADSC#
OE#
BWE#
CS#
MODE
ZZ
BW
c#
BW
b#
BLOCK DIAGRAM
512K x 18
SSRAM
DQ
c
,
DQP
c
DQ
b
,
DQP
b
512K x 18
SSRAM
DQ
a
,
DQP
a
DQ
d
,
DQP
d
* Enable on pins C7 and R7 are options for the three CS# density only.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2004
Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN DESCRIPTION
x36
CK
4P
4N
2A, 2C, 2R, 2B
3A, 3B, 3C, 3T
4T, 5A, 5B, 5C,
5T, 6A, 6B, 6C, 6R
5L
5G
3G
3L
4M
4H
4K
4E
7T
4F
4G
Symbol
Input
SA0
SA1
SA
Type
Pulse
Input
Description
WED2DL36513V
The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CK.
BWa
BWb
BWc
BWd
BWE
GW
CLK
CS
ZZ
OE
ADV
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written
and must meet the setup and hold times around the rising edge of CK. A byte write enable is
LOW for a WRITE cycle and HIGH for a READ cycle.
BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;
BWd# controls DQd’s and DQPd.
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the
setup and hold times around the rising edge of CK.
Global Write: This active LOW input allows a full 36- bit WRITE to occur independent of the BWE#
and BWx# lines and mustmeet the setup and hold times around the rising edge of CK.
Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs
on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the
internal use of ADSP#. CS# is sampled only when a new external address is loaded.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby
mode in which all data in the memory array is retained. When active, all other inputs are ignored.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
Synchronous Address Advance: This active LOW input is used to advance the internal burst counter,
controlling burst access after the external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of correct address during a WRITE
cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated.
Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing
a new external address to be registered. A READ is performed using the new address, independent of
the byte write enables and ADSC#, but dependent upon CS#, CS2# and CS2#. ADSP# is ignored if CS# is
HIGH. Powerdown state is entered if CS2# is LOW or CS2# is HIGH.
Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing
a new external address to be registered. A READ or WRITE is performed using the new address if CS#
is LOW. ADSC# is also used to place the chip into power-down state when CS# is HIGH.
Mode: This input selects the burst sequence. A LOW on MODE selects “linear burst.” NC or HIGH on
this input selects “interleaved burst.” Do not alter input state while device is operating.
SRAM Data I/Os: Byte “a” is DQa’s; Byte “b” is DQb’s; Byte “c” is DQc’s;
Byte “d” is DQd’s. Input data must meet setup and hold times around rising edge of CK.
Input
Input
Input
Input
Input
Input
Input
4A
ADSP
Input
4B
ADSC
Input
3R
(a) 6K, 6L, 6M, 6N,
7K, 7L, 7N, 7P
(b) 6E, 6F, 6G, 6H,
7D, 7E, 7G, 7H
(c) 1D, 1E, 1G, 1H
2E, 2F, 2G, 2H
(d) 1K, 1L, 1N, 1P,
2K, 2L, 2M, 2N
6P
6D
2D
2P
2J, 4C, 4J, 4R, 6J
1A, 1F, 1J, 1M 1U
7A, 7F, 7J, 7M, 7U
3D, 3E, 3F, 3H, 3K,
3M, 3N, 3P, 5D, 5E,
5F, 5H, 5K, 5M, 5N,
5P
2U
3U
4U
5U
MODE
DQa
DQb
DQc
DQd
DQPa
DQPb
DQPc
DQPd
V
CC
V
CCQ
V
SS
Input
Input/
Output
Input/
Output
Byte “a” Parity is DQPa; Byte “b” Parity is DQPb; Byte “c” Parity is DQPc;
Byte “d” Parity is DQPd.
Supply
Supply
Supply
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating
Conditions for range.
Ground: GND.
T
MS
T
DI
T
DO
T
CK
Input
Input
Output
Input
Scan Test Mode Select
Scan Test Data In
Scan Test Data Out
Scan Test Clock
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2004
Rev. 4
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
INTERLEAVED BURST TABLE
(MODE = NC OR HIGH)
First Address
External
X...X00
X...X01
X...X10
X...X11
Second Address
Internal
X...X01
X....X00
X...X11
X...X10
Third Address
Internal
X...X10
X...X11
X...X00
X...X01
Fourth Address
Internal
X...X11
X...X10
X...X01
X...X00
First Address
External
X...X00
X...X01
X...X10
X...X11
WED2DL36513V
INTERLEAVED BURST TABLE
(MODE = LOW)
Second Address
Internal
X...X01
X....X10
X...X11
X...X00
Third Address
Internal
X...X10
X...X11
X...X00
X...X01
Fourth Address
Internal
X...X11
X...X00
X...X01
X...X10
TRUTH TABLE
Function
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
Deselected Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Address
Used
None
None
None
None
None
None
External
External
External
External
External
Next
Next
Next
Next
Next
Next
Current
Current
Current
Current
Current
Current
CS#
H
L
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
CS2#
X
X
H
X
H
X
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
CS2
X
L
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
ZZ
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
ADSP# ADSC#
X
L
L
H
H
X
L
L
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
X
X
L
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
ADV#
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
L
H
H
H
H
H
H
WRITE
X
X
X
X
X
X
X
X
L
H
H
H
H
H
H
L
L
H
H
H
H
L
L
OE#
X
X
X
X
X
X
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
CK
L-H
L-H
L-H
L-H
L-H
X
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
DQ
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Q
High-Z
D
Q
High-Z
Q
High-Z
Q
High-Z
D
D
Q
High-Z
Q
High-Z
D
D
NOTES:
1. X means “Don’t Care.”
——
means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE = H for all BWx#, BWE#, GW#
HIGH.
3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s and DQPc. BWd# enables WRITEs to DQd’s and
DQPd.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CK, a WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for
the subsequent L-H edge of CK. Refer to WRITE timing diagram for clarification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2004
Rev. 4
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PARITAL TRUTH TABLE - WRITE COMMANDS
Function
Read
Read
Write Byte “a”
Write All Bytes
Write All Bytes
GW#
H
H
H
H
L
BWE#
H
L
L
L
X
BWa#
X
H
L
L
X
BWb#
X
H
H
L
X
BWc#
X
H
H
L
X
BWd#
X
H
H
L
X
Voltage on V
CC
Supply relative to V
SS
Voltage on V
CCQ
Supply relative to V
SS
V
IN
(DQx)
V
IN
(Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
WED2DL36513V
ABSOLUTE MAXIMUM RATINGS*
-0.5V to +4.6V
-0.5V to +4.6V
-0.5V to V
CCQ
+0.5V
-0.5V to V
CC
+0.5V
+55°C to +125°C
100 mA
NOTE: Using BWE and BWa through BWd, any one or more bytes may be written.
* Stress greater than those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
ELECTRICAL CHARACTERISTICS
Description
Input High (Logic 1)Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Ouptut Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
Symbol
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
V
CC
V
CCQ
0V ≤ V
IN
≤ V
CC
Output(s) disabled, 0V ≤ V
IN
≤ V
CC
I
OH
= -4.0mA
I
OL
= 8.0mA
Conditions
Min
2.0
-0.3
-1.0
-1.0
2.4
—
3.135
3.135
Max
Vdd +0.3
0.8
1.0
1.0
—
0.4
3.6
3.6
Units
V
V
µA
µA
V
V
V
V
1
1
1
Notes
1
1
2
NOTES:
1. All voltages referenced to V
SS
(GND).
2. MODE has an internal pull-up, and input leakage is higher.
DC CHARACTERISTICS
Description
Power Supply
Current: Operating
CMOS Standby
TTL Standby
Clock Running
Symbol
I
DD
I
SB2
I
SB3
I
SB4
Conditions
Device selected; All inputs ≤ V
IL
or V
IH
; Cycle time t
KC
MIN;
V
CC
= MAX; Outputs open
Device deselected; V
CC
= MAX; All inputs ≤ V
SS
+ 0.2
or V
CC
- 0.2; All inputs static; CK frequency = 0
Device deselected; V
CC
= MAX; All inputs ≤ V
IL
or V
IH
;
All inputs static; CLD frequency = 0
Device deselected; V
CC
= MAX; All inputs ≤ V
SS
+ 0.2
or V
CC
-0.2; Cycle time t
KC
MIN
10
20
80
Typ
200*
MHz
TBD
20
40
TBD
166
MHz
700
20
40
180
150
MHz
620
20
40
160
133
MHz
560
20
40
140
Units
mA
mA
mA
mA
Notes
1,2,3
2,3
2,3
2,3
* Advanced Information
NOTES:
1. I
DD
is specified with no output current and increases with faster cycle times. I
DD
increases with faster cycle times and greater output loading.
2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode).
3. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
BGA CAPACITANCS
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTE:
1. This parameter is sampled.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2004
Rev. 4
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Conditions
Ta = 25°C; f = 1MHz
Ta = 25°C; f = 1MHz
Ta = 25°C; f = 1MHz
Ta = 25°C; f = 1MHz
Symbol
Ci
Co
Ca
Cck
Typ
3
4
3
2.5
Max
4
5
5
4
Units
pF
pF
pF
pF
Notes
1
1
1
1
White Electronic Designs
AC CHARACTERISTICS (WED2DL36513V)
Parameter
Clock
Clock Cycle Time
Clock Frequency
Clock HIGH Time
Clock LOW Time
Output Times
Clock to output valid
Clock to output invalid (2)
Clock to output on Low-Z (2,3,4)
Clock to output in High-Z (2,3,4)
OE# to output valid (5)
OE# to output in Low-Z (2,3,4)
OE# to output in High Z (2,3,4)
Setup Times
Address (6,7)
Address status (ADSC#, ADSP#) (6,7)
Address advance (ADV#) (6,7)
Write signals (BWa#-BWd#, BWE#, GW#) (6,7)
Data-in (6,7)
Chip enables (CS#, CS2#, CS2) (6,7)
Hold Times
Address (6,7)
Address status (ADSC#, ADSP#) (6,7)
Address advance (ADV#) (6,7)
Write Signals (BWa#-BWd#, BWE#, GW#) (6,7)
Data-in (6,7)
Chip Enables (CS#, CS2#, CS2) (6,7)
Symbol
200MHz
Min
5.0
200
2.0
2.0
3.0
1.25
0
3.0
3.0
0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0
3.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1.25
0
3.5
3.5
0
2.4
2.4
3.5
1.25
0
Max
166MHz
Min
6.0
166
2.6
2.6
Max
150MHz
Min
6.6
WED2DL36513V
133MHz
Min
7.5
Max
Max
Units
t
KC
t
KF
t
KH
t
KL
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
t
AS
t
ADSS
t
AAS
t
WS
t
DS
t
CSS
t
AH
t
ADSH
t
AAH
t
WH
t
DH
t
CSH
150
2.6
2.6
3.8
1.5
0
3.8
3.8
0
3.8
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
133
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.0
4.0
4.0
4.0
NOTES:
1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V I/0 and Figure 3 for 2.5V I/0 unless otherwise noted.
2. This parameter is measured with output load as shown in Figure 2 for 3.3V I/0 and Figure 4 for 2.5V I/0.
3. This parameter is sampled.
4. Transition is measured ±500mV from steady state voltage.
5. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
6. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH
and ADSC# or ADV# LOW or ADSP# LOW for the required setup and hold times.
7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CK when either ADSP# or ADSC# is LOW and chip enabled. All
other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CK) when the chip is enabled. Chip enable must be valid at each
rising edge of CK when either ADSP# or ADSC# is LOW to remain enabled.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
November 2004
Rev. 4
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
微控制器 MCU
