The WEDC SyncBurst - SRAM family employs high-speed,
low-power CMOS designs that are fabricated using an
advanced CMOS process. WEDC’s 32Mb SyncBurst
SRAMs integrate two 1M x 18 SRAMs into a single BGA
package to provide 1M x 36 configuration. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single-clock input (CK). The NBL or No
Bus Latency Memory utilizes all the bandwidth in any
combination of operating cycles. Address, data inputs, and
all control signals except output enable and linear burst
order are synchronized to input clock. Burst order control
must be tied “High or Low.” Asynchronous inputs include the
sleep mode enable (ZZ). Output Enable controls the outputs
at any given time. Write cycles are internally self-timed and
initiated by the rising edge of the clock input. This feature
eliminates complex off-chip write pulse generation and
provides increased timing flexibility for incoming signals.
NOTE: NBL (No Bus Latency) is equivalent to ZBT™
PIN CONFIGURATION
(TOP VIEW)
4
SA
ADV#
V
CC
NC
CE1#
OE#
SA
WE#
V
CC
CK
NC
CKE#
SA1
SA0
V
CC
SA
NC
1
A
B
C
D
E
F
G
H
J
K
L
V
CCQ
SA
NC
DQc
DQc
V
CCQ
DQc
DQc
V
CCQ
DQd
DQd
2
SA
CE2
SA
DQPc
DQc
DQc
DQc
DQc
V
CC
DQd
DQd
DQd
DQd
DQPd
SA
NC
NC
3
SA
SA
SA
V
SS
V
SS
V
SS
BWc#
V
SS
NC
V
SS
BWd#
V
SS
V
SS
V
SS
LBO#
SA
NC
5
SA
SA
SA
V
SS
V
SS
V
SS
BWb#
V
SS
NC
V
SS
BWa#
V
SS
V
SS
V
SS
NC
SA
NC
6
SA
CE2#
SA
DQPb
DQb
DQb
DQb
DQb
V
CC
DQa
DQa
DQa
DQa
DQPa
SA
NC
NC
7
V
CCQ
NC
NC
DQb
DQb
V
CCQ
DQb
DQb
V
CCQ
DQa
DQa
V
CCQ
DQa
DQa
NC
ZZ
V
CCQ
CK
CKE#
ADV#
LBO#
CE1#
CE2
CE2#
OE#
WE#
ZZ
BLOCK DIAGRAM
BWa#
BWb#
BWc#
BWd#
1M x 18
CK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
CK
CKE#
ADV#
LBO#
CS1#
CS2
CS2#
OE#
WE#
ZZ
1M x 18
Address Bus
(SA0 - SA19)
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
M
V
CCQ
N
DQd
P
R
T
U
DQd
NC
NC
V
CCQ
DQa - DQd
DQPa - DQPd
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
The WED2ZL361MS is an NBL SSRAM designed to sus-
tain 100% bus bandwidth by eliminating turnaround cycle
when there is transition from Read to Write, or vice versa.
All inputs (with the exception of OE#, LBO# and ZZ) are
synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV# input. Subsequent burst addresses can be internally
generated by the burst advance pin (ADV#). ADV# should
be driven to Low once the device has been deselected in
order to load a new address for next operation.
Clock Enable (CKE#) pin allows the operation of the chip to
be suspended as long as necessary. When CKE# is high,
all synchronous inputs are ignored and the internal device
registers will hold their previous values. NBL SSRAM
latches external address and initiates a cycle when CKE#
and ADV# are driven low at the rising edge of the clock.
Output Enable (OE#) can be used to disable the output
at any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the ad-
dress inputs are latched in the address register, CKE# is
driven low, the write enable input signals WE# are driven
high, and ADV# driven low. The internal array is read
between the first rising edge and the second rising edge
of the clock and the data is latched in the output register.
At the second clock edge the data is driven out of the
SRAM. During read operation OE# must be driven low for
the device to drive out the requested data.
WED2ZL361MS
FUNCTION DESCRIPTION
Write operation occurs when WE# is driven low at the ris-
ing edge of the clock. BW#[d:a] can be used for byte write
operation. The pipe-lined NBL SSRAM uses a late-late write
cycle to utilize 100% of the bandwidth. At the first rising edge
of the clock, WE# and address are registered, and the data
associated with that address is required two cycle later.
Subsequent addresses are generated by ADV# High for
the burst access as shown below. The starting point of the
burst seguence is provided by the external address. The
burst address counter wraps around to its initial state upon
completion. The burst sequence is determined by the state
of the LBO# pin. When this pin is low, linear burst sequence
is selected. And when this pin is high, Interleaved burst
sequence is selected.
During normal operation, ZZ must be driven low. When ZZ
is driven high, the SRAM will enter a Power Sleep Mode
after 2 cycles. At this time, internal state of the SRAM is
preserved. When ZZ returns to low, the SRAM operates
after 2 cycles of wake up time.
BURST SEQUENCE TABLE
(INTERLEAVED BURST, LBO# = HIGH)
(LINEAR BURST, LBO# = LOW)
LBO# Pin
High
Case 1
A1
0
0
1
1
A0
0
1
0
1
Case 2
A1
0
0
1
1
A0
1
0
1
0
Case 3
A1
1
1
0
0
A0
0
1
0
1
Case 4
A1
1
1
0
0
A0
1
0
1
0
LBO# Pin
High
Case 1
A1
0
0
1
1
A0
0
1
0
1
Case 2
A1
0
1
1
0
A0
1
0
1
0
Case 3
A1
1
1
0
0
A0
0
1
0
1
Case 4
A1
1
0
0
1
A0
1
0
1
0
First Address
↓
Fourth Address
First Address
↓
Fourth Address
NOTE 1: LBO# pin must be tied to High or Low, and Floating State must not be
allowed.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
TRUTH TABLES
SYNCHRONOUS TRUTH TABLE
CEx# ADV
H
L
X
H
L
L
X
H
L
L
X
H
L
L
X
H
L
L
X
H
X
X
WE#
X
X
H
X
H
X
L
X
L
X
X
BWx#
X
X
X
X
X
X
L
L
H
H
X
OE#
X
X
L
L
H
H
X
X
X
X
X
CKE#
L
L
L
L
L
L
L
L
L
L
H
CK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
Address Accessed
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
WED2ZL361MS
Operation
Deselect
Continue Deselect
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
Ignore Clock
NOTES:
1.
X means “Don’t Care.”
2.
The rising edge of clock is symbolized by (
↑
)
3.
A continue deselect cycle can only be entered if a deselect cycle is executed first.
4.
WRITE# = L means Write operation in WRITE TRUTH TABLE.
WRITE# = H means Read operation in WRITE TRUTH TABLE.
5.
Operation finally depends on status of asynchronous input pins (ZZ and OE#).
6.
CEx# refers to the combination of CE1#, CE2 and CE2#.
WRITE TRUTH TABLE
WE#
H
L
L
L
L
L
L
BWa# BWb# BWc# BWd#
X
X
X
X
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
L
L
H
H
H
H
Operation
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
NOTES:
1.
X means “Don’t Care.”
2.
All inputs in this table must meet setup and hold time around the
rising edge of CK (
↑
).
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Supply Relative to V
SS
Vin (DQx)
Vin (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
-0.3V to +3.6V
-0.3V to +3.6V
-0.3V to +3.6V
-55°C to +125°C
100mA
WED2ZL361MS
*Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.
(Voltage Referenced to: V
SS
= OV, T
A
= 0°C; Commercial or -40°C ≤ T
A
≤ 85°C; Industrial)
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
V
IH
V
IL
I
LI
I
LO
V
OH
V
OL
V
CC
0V ≤ V
IN
≤ V
CC
Output(s) Disabled, 0V ≤ V
IN
≤ V
CC
I
OH
= -1.0mA
I
OL
= 1.0mA
Conditions
Min
1.7
-0.3
-5
-5
2.0
–
2.375
Max
V
CC
+0.3
0.7
5
5
–
0.4
2.625
Units
V
V
µA
µA
V
V
V
1
1
1
Notes
1
1
2
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1. All voltages referenced to V
SS
(GND)
2. ZZ pin has an internal pull-up, and input leakage is higher.
DC CHARACTERISTICS
Description
Power Supply
Current: Operating
Power Supply
Current: Standby
Power Supply
Current: Current
Clock Running
Standby Current
Symbol
I
DD
I
SB2
Conditions
Device Selected; All Inputs ½ V
IL
or ½ V
IH
; Cycle
Time = T
CYC
MIN; V
CC
= MAX; Output Open
Device Deselected; V
CC
= MAX; All Inputs½ V
SS
+ 0.2
or V
CC
- 0.2; All Inputs Static; CK Frequency = 0;
ZZ ½ V
IL
Device Selected; All Inputs ½ V
IL
or ½ V
IH
; Cycle
Time = T
CYC
MIN; V
CC
= MAX; Output Open;
ZZ ½ V
CC
- 0.2V
Device Deselected; V
CC
= MAX; All Inputs
½ V
SS
+ 0.2 or V
CC
- 0.2; Cycle Time = T
CYC
MIN; ZZ ½ V
IL
30
Typ
250
MHz
900
60
200
MHz
800
60
166
MHz
690
60
133
MHz
580
60
Units
mA
mA
Notes
1, 2
2
I
SB3
20
40
40
40
40
mA
2
I
SB4
150
140
130
100
mA
2
NOTES:
1.
I
DD
is specified with no output current and increases with faster cycle times.
I
DD
increases with faster cycle times and greater output loading.
2.
Typical values are measured at 2.5V, 25°C, and 10ns cycle time.
BGA CAPACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTES:
1.
This parameter is sampled.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
Symbol
C
I
C
O
C
A
C
CK
Conditions
T
A
= 25°C; f = 1MH
Z
T
A
= 25°C; f = 1MH
Z
T
A
= 25°C; f = 1MH
Z
T
A
= 25°C; f = 1MH
Z
Typ
5
6
5
3
Max
7
8
7
5
Units
pF
pF
pF
pF
Notes
1
1
1
1
White Electronic Designs
AC CHARACTERISTICS
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
ZZ High to Power Down
ZZ Low to Power Up
Symbol
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
CH
t
CL
t
AS
t
CES
t
DS
t
WS
t
ADVS
t
CSS
t
AH
t
CEH
t
DH
t
WH
t
ADVH
t
CSH
t
PDS
t
PUS
250MHz
Min
4.0
--
--
1.5
1.5
0.0
--
--
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
2
2
2.6
2.6
--
--
--
2.6
2.6
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
225MHz
Min
4.4
--
--
1.5
1.5
0.0
--
--
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
2.8
2.8
--
--
--
2.8
2.8
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
200MHz
Min
5.0
--
--
1.5
1.5
0.0
--
--
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
3.0
3.0
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
166MHz
Min
6.0
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
3.5
3.5
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
WED2ZL361MS
150MHz
Min
6.7
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
3.8
3.8
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
133MHz
Min
7.5
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
4.2
4.2
--
--
--
3.5
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is sampled valid. All other
synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both cases must
meet setup and hold times.
(0 ≤ T
A
≤ 70°C, V
CC
= 2.5V ± 5%; Commercial or -40°C ≤ Ta ≤ 85°C; V
CC
= 2.5V ± 5%; Industrial)
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
Value
0 to 2.5V
1.0V/ns
1.25V
See Output Load (A)
AC TEST CONDITIONS
OUTPUT LOAD (A)
Dout
Zo=50Ω
RL=50Ω
VL=1.25V
30pF*
OUTPUT LOAD (B)
(for t
LZC
, t
LZOE
, t
HZOE
, and t
HZC
)
+2.5V
Dout
1538Ω
1667Ω
5pF*
*Including Scope and Jig Capacitance
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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