integrate two 1M x 18 SRAMs into a single BGA package
to provide 1M x 36 configuration. All synchronous inputs
pass through registers controlled by a positive-edge-
triggered single-clock input (CLK). The NBL or No Bus
Latency Memory utilizes all the bandwidth in any combi-
nation of operating cycles. Address, data inputs, and all
control signals except output enable and linear burst
order are synchronized to input clock. Burst order con-
trol must be tied “High or Low.” Asynchronous inputs
include the sleep mode enable (ZZ). Output Enable
controls the outputs at any given time. Write cycles are
internally self-timed and initiated by the rising edge of
the clock input. This feature eliminates complex off-chip
write pulse generation and provides increased timing
flexibility for incoming signals.
NOTE: NBL (No Bus Latency) is equivalent to ZBT™.
(VDD, VDDQ)
n
Snooze Mode for reduced-standby power
n
Individual Byte Write control
n
Clock-controlled and registered addresses, data I/Os
and control signals
n
Burst control (interleaved or linear burst)
n
Packaging:
• 119-bump BGA package
• JEDEC Pin Configuration
n
Low capacitive bus loading
FIG. 1
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC
NC
DQ
c
DQ
c
V
DDQ
DQ
c
DQ
c
V
DDQ
DQ
d
DQ
d
V
DDQ
DQ
d
DQ
d
NC
NC
V
DDQ
PIN CONFIGURATION
(TOP VIEW)
2
SA
CE2
SA
DQP
c
DQ
c
DQ
c
DQ
c
DQ
c
V
DD
DQ
d
DQ
d
DQ
d
DQ
d
DQP
d
SA
NC
NC
3
SA
SA
SA
V
SS
V
SS
V
SS
BW
c
V
SS
NC
V
SS
BW
d
V
SS
V
SS
V
SS
LBO
SA
NC
4
SA
ADV
V
DD
NC
CE1
OE
SA
WE
V
DD
CLK
NC
CKE
SA1
SA0
V
DD
SA
NC
5
SA
SA
SA
V
SS
V
SS
V
SS
BW
b
V
SS
NC
V
SS
BW
a
V
SS
V
SS
V
SS
NC
SA
NC
6
SA
CE2
SA
DQP
b
DQ
b
DQ
b
DQ
b
DQ
b
V
DD
DQ
a
DQ
a
DQ
a
DQ
a
DQP
a
SA
SA
NC
7
BWc
BWd
BWa
BWb
BLOCK DIAGRAM
V
DDQ
NC
NC
DQ
b
DQ
b
V
DDQ
DQ
b
DQ
b
V
DDQ
DQ
a
DQ
a
V
DDQ
DQ
a
DQ
a
NC
ZZ
V
DDQ
Address Bus
(SA
0
– SA
19
)
1M x 18
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
1M x 18
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa
–
DQd
DQPa
–
DQPd
October 2002 Rev. 1
ECO # 15465
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
FUNCTION DESCRIPTION
The WED2ZL361MSJ is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycles when there is transition from Read to Write, or
vice versa. All inputs (with the exception of OE, LBO
and ZZ) are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been
deselected in order to load a new address for next
operation.
The clock Enable (CKE) pin allows the operation of the
chip to be suspended as long as necessary. When CKE
is high, all synchronous inputs are ignored and the
internal device registers will hold their previous values.
NBL SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
Output Enable (OE) can be used to disable the output
at any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE is
driven low, the write enable input signals WE are driven
high, and ADV driven low. The internal array is read
between the first rising edge and the second rising edge
of the clock and the data is latched in the output register.
At the second clock edge the data is driven out of the
SRAM. During read operation OE must be driven low for
the device to drive out the requested data.
WED2ZL361MSJ
Write operation occurs when WE is driven low at the
rising edge of the clock. BW[d:a] can be used for byte
write operation. The pipe-lined NBL SSRAM uses a late-
late write cycle to utilize 100% of the bandwidth. At the
first rising edge of the clock, WE and address are regis-
tered, and the data associated with that address is
required two cycles later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst sequence is provided by the external address.
The burst address counter wraps around to its initial state
upon completion. The burst sequence is determined by
the state of the LBO pin. When this pin is low, linear burst
sequence is selected. When this pin is high, interleaved
burst sequence is selected.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
BURST SEQUENCE TABLE
(Interleaved Burst, LBO = High)
Case 1
LBO Pin High A1
First Address
0
0
1
Fourth Address
NOTES
1. LBO pin must be tied to High or Low, and Floating State must not be allowed.
2. LBO cannot change after initial power up.
White Electronic Designs Corporation Westborough MA (508) 366-5151
2
(Linear Burst, LBO = Low)
Case 1
LBO Pin High A1
First Address
0
0
1
Fourth Address
1
A0
0
1
0
1
Case 2
A1
0
1
1
0
1
0
1
0
Case 3
A0
0
1
0
1
1
1
0
0
Case 4
A1
1
0
0
1
A0
1
0
1
0
A0 A1
Case 2
0
0
1
1
1
0
1
0
Case 3
1
1
0
0
0
1
0
1
Case 4
A0
1
0
1
0
1
1
0
0
A0 A1 A0 A1
0
1
0
1
A0 A1
1
White Electronic Designs
TRUTH TABLES
S
YNCHRONOUS
T
RUTH
T
ABLE
WED2ZL361MSJ
CEx
H
X
L
X
L
X
L
X
L
X
X
NOTES:
1.
2.
3.
4.
5.
6.
ADV
L
H
L
H
L
H
L
H
L
H
X
WE
X
X
H
X
H
X
L
X
L
X
X
BWx
X
X
X
X
X
X
L
L
H
H
X
OE
X
X
L
L
H
H
X
X
X
X
X
CKE
L
L
L
L
L
L
L
L
L
L
H
CLK Address Accessed
á
á
á
á
á
á
á
á
á
á
á
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
Operation
Deselect
Continue Deselect
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
Ignore Clock
X means “Don’t Care.”
The rising edge of clock is symbolized by (
á
)
A continue deselect cycle can only be entered if a deselect cycle is executed first.
WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
Operation finally depends on status of asynchronous input pins (ZZ and OE).
CEx refers to the combination of CE1, CE2 and CE2.
W
RITE
T
RUTH
T
ABLE
WE
H
L
L
L
L
L
L
NOTES:
1.
2.
BWa
X
L
H
H
H
L
H
BWb
X
H
L
H
H
L
H
BWc
X
H
H
L
H
L
H
BWd
X
H
H
H
L
L
H
Operation
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
X means “Don’t Care.”
All inputs in this table must meet setup and hold time around the rising edge of CLK (á).
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
Voltage on V
DD
Supply Relative to VSS
VIN (DQx)
VIN (Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
*
WED2ZL361MSJ
-0.3V to +3.6V
-0.3V to +3.6V
-0.3V to +3.6V
-55°C to +125°C
100mA
Stress greater than those listed under “Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
(V
OLTAGE
R
EFERENCED TO
: V
SS
= OV, T
A
= 0°C
TO
70°C; C
OMMERCIAL OR
T
A
= -40°C
TO
+85°C; I
NDUSTRIAL
)
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
NOTES:
1. All voltages referenced to V
SS
(GND)
2. ZZ pin has an internal pull-up, and input leakage is higher.
Symbol
Conditions
V
IH
V
IL
ILI
0V
£
V
IN
£
V
DD
I
LO
Output(s) Disabled, 0V
£
V
IN
£
V
DD
V
OH
I
OH
= -1.0mA
V
OL
I
OL
= 1.0mA
V
DD
Min
1.7
-0.3
-5
-5
2.0
---
2.375
Max
V
DD
+0.3
0.7
5
5
---
0.4
2.625
Units
V
V
µA
µA
V
V
V
Notes
1
1
2
1
1
1
DC C
HARACTERISTICS
Description
Symbol Conditions
Power Supply
I
DD
Device Selected; All Inputs
£
V
IL
or
³
V
IH
; Cycle
Current: Operating
Time = T
CYC
MIN; V
DD
= MAX; Output Open
Power Supply
I
SB2
Device Deselected; V
DD
= MAX; All Inputs
Current: Standby
£
V
SS
+ 0.2 or VDD - 0.2; All Inputs Static;
CLK Frequency = 0; ZZ
£
VIL
Power Supply
I
SB3
Device Selected; All Inputs
£
V
IL
or
³
V
IH
; Cycle
Current: Current
Time = T
CYC
MIN; V
DD
= MAX; Output Open;
ZZ
³
V
DD
- 0.2V
Clock Running
I
SB4
Device Deselected; V
DD
= MAX; All Inputs
Standby Current
£
V
SS
+ 0.2 or V
DD
- 0.2; Cycle Time = T
CYC
MIN; ZZ
£
V
IL
NOTES:
1.
2.
I
DD
is specified with no output current and increases with faster cycle times.
I
DD
increases with faster cycle times and greater output loading.
Typical values are measured at 2.5V, 25°C, and 10ns cycle time.
250 200 166 133
Typ MHz MHz MHz MHz Units Notes
900 800 690 580
mA
1, 2
30
60
60
60
60
mA
2
20
40
40
40
40
mA
2
150
140
130
100
mA
2
BGA C
APACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTE:
1. This parameter is sampled.
4
Symbol
C
I
C
O
C
A
C
CK
T
A
T
A
T
A
T
A
Conditions
= 25°C; f = 1MHz
= 25°C; f = 1MHz
= 25°C; f = 1MHz
= 25°C; f = 1MHz
Typ
5
6
5
3
Max
7
8
7
5
Units
pF
pF
pF
pF
Notes
1
1
1
1
White Electronic Designs Corporation Westborough MA (508) 366-5151
White Electronic Designs
AC C
HARACTERISTICS
Symbol
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
ZZ High to Power Down
ZZ Low to Power Up
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
CH
t
CL
t
AS
t
CES
t
DS
t
WS
t
ADVS
t
CSS
t
AH
t
CEH
t
DH
t
WH
t
ADVH
t
CSH
t
PDS
t
PUS
250MHz
Min
4.0
--
--
1.5
1.5
0.0
--
--
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
2
2
2.6
2.6
--
--
--
2.6
2.6
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
225MHz
Min
4.4
--
--
1.5
1.5
0.0
--
--
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
2.8
2.8
--
--
--
2.8
2.8
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
200MHz
Min
5.0
--
--
1.5
1.5
0.0
--
--
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
3.0
3.0
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
166MHz
Min
6.0
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
3.5
3.5
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
WED2ZL361MSJ
150MHz
Min
6.7
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
3.8
3.8
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
133MHz
Min
7.5
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
4.2
4.2
--
--
--
3.5
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
Max
NOTES:
1.
All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is sampled valid. All other
synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low.
A Read cycle is defined by WE High with ADV Low. Both cases must meet setup and hold times.
AC T
EST
C
ONDITIONS
(T
A
= 0
TO
70°C, VDD = 2.5V ± 5%; C
OMMERCIAL OR
T
A
= -40°C
TO
+85°C, VDD = 2.5V ± 5%; I
NDUSTRIAL
)
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
O
UTPUT
L
OAD
(A)
Dout
Zo=50
RL=50
VL=1.25V
30pF*
Value
0 to 2.5V
1.0V/ns
1.25V
See Output Load (A)
O
UTPUT
L
OAD
(B)
(
FOR
t
LZC
, t
LZOE
, t
HZOE
,
AND
t
HZC
)
+2.5V
Dout
1538
1667
5pF*
*Including Scope and Jig Capacitance
5
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
微控制器 MCU
