White Electronic Designs
WED2ZL361MV
1Mx36 Synchronous Pipeline Burst NBL SRAM
FEATURES
n
Fast clock speed: 166, 150, 133, and 100MHz
n
Fast access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
n
Fast OE access times: 3.5ns, 3.8ns, 4.2ns, and 5.0ns
n
Single +3.3V ± 5% power supply (V
DD
)
n
Snooze Mode for reduced-standby power
n
Individual Byte Write control
n
Clock-controlled and registered addresses, data
I/Os and control signals
n
Burst control (interleaved or linear burst)
n
Packaging:
119-bump BGA package
n
Low capacitive bus loading
DESCRIPTION
The WEDC SyncBurst - SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process. WEDCs 32Mb
SyncBurst SRAMs integrate two 1M x 18 SRAMs into a
single BGA package to provide 1M x 36 configuration. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single-clock input (CLK).
The NBL or No Bus Latency Memory utilizes all the band-
width in any combination of operating cycles. Address,
data inputs, and all control signals except output en-
able and linear burst order are synchronized to input
clock. Burst order control must be tied High or Low.
Asynchronous inputs include the sleep mode enable
(ZZ). Output Enable controls the outputs at any given
time. Write cycles are internally self-timed and initiated
by the rising edge of the clock input. This feature elimi-
nates complex off-chip write pulse generation and pro-
vides increased timing flexibility for incoming signals.
FIG. 1
P
IN
C
ONFIGURATION
(TOP VIEW)
B
LOCK
D
IAGRAM
5
SA
SA
SA
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
SA
NC
6
SA
CE
2
SA
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
SA
NC
NC
7
V
DD
NC
NC
DQ
B
DQ
B
V
DD
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
V
DD
DQ
A
DQ
A
NC
ZZ
V
DD
Address Bus
(SA
0
SA
19
)
1M x 18
CLK
CKE
ADV
LBO
CE1
CE2
CE2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
CLK
CKE
ADV
LBO
CS1
CS2
CS2
OE
WE
ZZ
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DD
SA
NC
DQ
C
DQ
C
V
DD
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
V
DD
DQ
D
DQ
D
NC
NC
V
DD
2
SA
CE
2
SA
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
SA
NC
NC
3
SA
SA
SA
V
SS
V
SS
V
SS
BW
C
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
LBO
SA
NC
4
SA
ADV
V
DD
NC
CE
1
OE
SA
WE
V
DD
CLK
NC
CKE
SA
1
SA
0
V
DD
SA
NC
BWc
BWd
1M x 18
BWa
BWb
-
DQc, DQd
DQPc, DQPd
DQa, DQb
DQPa, DQPb
DQa
DQPa
-
DQd
-
DQPd
December 2002 Rev. 2
ECO #15834
1
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
FUNCTION DESCRIPTION
The WED2ZL361MV is an NBL SSRAM designed to
sustain 100% bus bandwidth by eliminating turnaround
cycle when there is transition from Read to Write, or vice
versa. All inputs (with the exception of OE, LBO and ZZ)
are synchronized to rising clock edges.
All read, write and deselect cycles are initiated by the
ADV input. Subsequent burst addresses can be inter-
nally generated by the burst advance pin (ADV). ADV
should be driven to Low once the device has been dese-
lected in order to load a new address for next operation.
Clock Enable (CKE) pin allows the operation of the chip
to be suspended as long as necessary. When CKE is
high, all synchronous inputs are ignored and the inter-
nal device registers will hold their previous values. NBL
SSRAM latches external address and initiates a cycle
when CKE and ADV are driven low at the rising edge of
the clock.
Output Enable (OE) can be used to disable the output at
any given time. Read operation is initiated when at the
rising edge of the clock, the address presented to the
address inputs are latched in the address register, CKE
is driven low, the write enable input signals WE are
driven high, and ADV driven low. The internal array is
read between the first rising edge and the second ris-
ing edge of the clock and the data is latched in the out-
put register. At the second clock edge the data is driven
out of the SRAM. During read operation OE must be
driven low for the device to drive out the requested data.
WED2ZL361MV
Write operation occurs when WE is driven low at the
rising edge of the clock. BW[d:a] can be used for byte
write operation. The pipe-lined NBL SSRAM uses a
late-late write cycle to utilize 100% of the bandwidth. At
the first rising edge of the clock, WE and address are
registered, and the data associated with that address
is required two cycle later.
Subsequent addresses are generated by ADV High for
the burst access as shown below. The starting point of
the burst seguence is provided by the external address.
The burst address counter wraps around to its initial
state upon completion. The burst sequence is deter-
mined by the state of the LBO pin. When this pin is low,
linear burst sequence is selected. And when this pin is
high, Interleaved burst sequence is selected.
During normal operation, ZZ must be driven low. When
ZZ is driven high, the SRAM will enter a Power Sleep
Mode after 2 cycles. At this time, internal state of the
SRAM is preserved. When ZZ returns to low, the SRAM
operates after 2 cycles of wake up time.
B
URST
S
EQUENCE
T
ABLE
(Interleaved Burst, LBO = High)
LBO Pin High
First Address
Fourth Address
Case 1
A1
A0
0
0
0
1
1
0
1
1
Case 2
A1
A0
0
1
0
0
1
1
1
0
Case 3
A1
A0
1
0
1
1
0
0
0
1
Case 4
A1
A0
1
1
1
0
0
1
0
0
(Linear Burst, LBO = Low)
LBO Pin High
First Address
Fourth Address
Case 1
A1
A0
0
0
0
1
1
0
1
1
Case 2
A1
A0
0
1
1
0
1
1
0
0
Case 3
A1
A0
1
0
1
1
0
0
0
1
Case 4
A1
A0
1
1
0
0
0
1
1
0
NOTE 1: LBO pin must be tied to High or Low, and Floating State
must not be allowed.
White Electronic Designs Corporation Westborough MA (508) 366-5151
2
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TRUTH TABLES
S
YNCHRONOUS
T
RUTH
T
ABLE
CEx
H
X
L
X
L
X
L
X
L
X
X
ADV
L
H
L
H
L
H
L
H
L
H
X
WE
X
X
H
X
H
X
L
X
L
X
X
BWx
X
X
X
X
X
X
L
L
H
H
X
OE
X
X
L
L
H
H
X
X
X
X
X
CKE
L
L
L
L
L
L
L
L
L
L
H
CLK
Address Accessed
N/A
N/A
External Address
Next Address
External Address
Next Address
External Address
Next Address
N/A
Next Address
Current Address
WED2ZL361MV
Operation
Deselect
Continue Deselect
Begin Burst Read Cycle
Continue Burst Read Cycle
NOP/Dummy Read
Dummy Read
Begin Burst Write Cycle
Continue Burst Write Cycle
NOP/Write Abort
Write Abort
Ignore Clock
NOTES:
1. X means Dont Care.
2. The rising edge of clock is symbolized by ( )
3. A continue deselect cycle can only be entered if a deselect cycle is executed first.
4. WRITE = L means Write operation in WRITE TRUTH TABLE.
WRITE = H means Read operation in WRITE TRUTH TABLE.
5. Operation finally depends on status of asynchronous input pins (ZZ and OE).
6. CEx refers to the combination of CE
1
, CE
2
and CE
2
.
W
RITE
T
RUTH
T
ABLE
WE
H
L
L
L
L
L
L
BWa
X
L
H
H
H
L
H
BWb
X
H
L
H
H
L
H
BWc
X
H
H
L
H
L
H
BWd
X
H
H
H
L
L
H
Operation
Read
Write Byte a
Write Byte b
Write Byte c
Write Byte d
Write All Bytes
Write Abort/NOP
NOTES:
1. X means Dont Care.
2. All inputs in this table must meet setup and hold time around the rising edge of
CLK ( ).
3
White Electronic Designs Corporation (508) 366-5151 www.whiteedc.com
White Electronic Designs
A
BSOLUTE
M
AXIMUM
R
ATINGS
*
Voltage on V
DD
Supply Relative to V
SS
V
IN
(DQx)
V
IN
(Inputs)
Storage Temperature (BGA)
Short Circuit Output Current
WED2ZL361MV
-0.3V to +4.6V
-0.3V to +4.6V
-0.3V to +4.6V
-65°C to +150°C
100mA
*Stress greater than those listed under Absolute Maximum Ratings: may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating condtions for extended periods may affect reliability.
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
V
OLTAGE
R
EFERENCED TO
:
V
SS
= 0V, T
A
= 0°C
TO
+70°C; C
OMMERCIAL OR
T
A
= -40°C
TO
+85°C; I
NDUSTRIAL
Description
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Symbol
Conditions
V
IH
V
IL
I
LI
0V
£
V
IN
£
V
DD
I
LO
Output(s) Disabled, 0V
£
V
IN
£
V
DD
V
OH
I
OH
= -4.0mA
V
OL
I
OL
= 8.0mA
V
DD
Min
2.0
-0.3
-5
-5
2.4
3.135
Max
V
DD
+0.5
0.8
5
5
0.4
3.465
Units
V
V
µA
µA
V
V
V
Notes
1
1
2
1
1
1
NOTES:
1. All voltages referenced to V
SS
(GND)
2. ZZ pin has an internal pull-up, and input leakage = ± 10µA.
DC C
HARACTERISTICS
Description
Power Supply
Current: Operating
Power Supply
Current: Standby
Power Supply
Current: Current
Clock Running
Standby Current
Symbol
I
DD
I
SB
2
Conditions
Device Selected; All Inputs
£
V
IL
or
³
V
IH
; Cycle
Time = T
CYC
MIN; V
DD
= MAX; Output Open
Device Deselected; V
DD
= MAX; All Inputs
£
V
SS
+ 0.2
or V
DD
- 0.2; All Inputs Static; CLK Frequency = 0;
ZZ
£
V
IL
I
SB
3
Device Selected; All Inputs
£
V
IL
or
³
V
IH
; Cycle
Time = T
CYC
MIN; V
DD
= MAX; Output Open;
ZZ
³
V
DD
- 0.2V
Device Deselected; V
DD
= MAX; All Inputs
30
60
60
60
60
mA
2
30
Typ
166
MHz
840
60
150
MHz
800
60
133
MHz
760
60
100
MHz
640
60
Units Notes
mA
mA
1, 2
2
I
SB
4
240
220
180
160
mA
2
£
V
SS
+ 0.2 or V
DD
- 0.2; Cycle Time = T
CYC
MIN; ZZ
£
V
IL
NOTES:
1. I
DD
is specified with no output current and increases with faster cycle times.
I
DD
increases with faster cycle times and greater output loading.
2. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.
BGA C
APACITANCE
Description
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
NOTES:
1. This parameter is sampled.
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4
Symbol
C
I
C
O
C
A
C
CK
Conditions
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
Typ
5
6
5
3
Max
7
8
7
5
Units
pF
pF
pF
pF
Notes
1
1
1
1
White Electronic Designs
AC C
HARACTERISTICS
Symbol
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
CH
t
CL
t
AS
t
CES
t
DS
t
WS
t
ADVS
t
CSS
t
AH
t
CEH
t
DH
t
WH
t
ADVH
t
CSH
166MHz
Min
6.0
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
3.5
3.5
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
150MHz
Min
6.7
--
--
1.5
1.5
0.0
--
--
2.5
2.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
3.8
3.8
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
WED2ZL361MV
133MHz
Min
7.5
--
--
1.5
1.5
0.0
--
--
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
4.2
4.2
--
--
--
3.5
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
100MHz
Min
10.0
--
--
1.5
1.5
0.0
--
--
3.0
3.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
5.0
5.0
--
--
--
3.5
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CLK) edges when ADV is sampled low and CEx is
sampled valid. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CLK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE low having been registered into the device at ADV Low. A Read cycle is defined by WE High with ADV Low.
Both cases must meet setup and hold times.
AC T
EST
C
ONDITIONS
T
A
= 0°C
TO
+70°C, V
DD
= 3.3V ± 5%; C
OMMERCIAL OR
T
A
= -40°C
TO
+85°C, V
DD
= 3.3V ± 5%; I
NDUSTRIAL
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
Value
0 to 3.0V
1.0V/ns
1.5V
See Output Load (A)
O
UTPUT
L
OAD
(A)
Dout
Zo=50Ω
RL=50Ω
VL=1.5V
30pF*
O
UTPUT
L
OAD
(B)
(
FOR
t
LZC
, t
LZOE
, t
HZOE
,
AND
t
HZC
)
+3.3V
Dout
353
Ω
3.9
Ω
5pF*
*Including Scope and Jig Capacitance
5
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