WED3EL7216S
SRAM,
WED3EL7216S, DDR SRAM, 2.5v CORE/ 2.5V IO
FEATURES
Advanced*
n
Core Supply Voltage = 2.5v +/- 0.2v
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IO Supply Voltage = 2.5v +/- 0.2v
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Bidirectional data strobe (DQS)
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Internal, pipelined, double data rate architecture
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n
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for a programmed number of locations, as defined by the
programmable burst command.
INITIALIZATION
Differential Clock Inputs
Positive edge; Command execution
Four internal banks for concurrent operation
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DLL for alignment of DQ and DQS transitions
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Data Mask (DM) for masking write data
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Programmable IOL/IOH
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n
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Programmable Burst length: 2,4, or 8
Auto Precharge option
Auto Refresh and Self Refresh Modes
GENERAL DESCRIPTION
The White Electronic Designs DDR SDRAM (x72/80) is a syn-
chronous dynamic random-access memory supporting data
transfer on each of the clock edges within a single cycle,
and is configured internally as a quad bank architecture
which supports concurrent operations.
The double data rate (DDR) architecture is referenced to as
a 2n-pre-fetch architecture with an interface designed to
transfer two data words per clock cycle. A single Read or
Write access consists of a single 2n-bit wide, one clock
cycle data transfer at the internal DRAM core and two cor-
responding n-bit wide, one half clock cycle data transfers
at the I/O pins.
The WED3EL7216S devices contain differential clock inputs;
the crossing of CK going through its voltage transition to a
high true, and CK\ going through its voltage transition to a
low true references a positive edge. Commands as well as
Address(s) and Control(s) are registered on positive edges,
Data is registered on both edges as well as Output Data is
referenced on both edges of the Clock.
Read and Write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue
DDR SDRAMs must be initialized via properly powering up.
Operation and use of this device outside of established
procedure(s) may result in undefined operation. Power must
be first applied to Vcc and VccQ simultaneously and then
Vref (and System Vtt) must be applied after VccQ in order
to avoid device latch-up. Vref may be applied any time af-
ter VccQ but is normally expected at coincidence with Vtt.
Except for CKE (clock enable) inputs are not recognized
as valid until after Vref is applied. CKE is an SSTL_2 input but
will detect an LVCMOS Low level after Vcc is applied. Main-
taining an LVCOMOS Low level on CLE during power-up is
required to ensure that the DQ and DQS outputs will be in
the HIGH-Z state where they will remain until driven in a
normal READ operation. Once the POWER SUPPLY, and REF-
ERENCE VOLTAGE is STABLE, the DDR SDRAM device re-
quires 200us delay prior to execution of a COMMAND se-
quence. Once the 200us delay requirement has been meet,
a DESELECT or NOP command should be applied, and CKE
should be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a LOAD
MODE REGISTER command is to be issued for the extended
mode register (enabling the DLL) followed by another LOAD
MODE REGISTER command to be issued to reset the DLL
and program the operating parameters. Two hundred (200)
clock cycles are required between the DLL reset and any
READ command. A PRECHARGE ALL command should then
be applied, placing the device in the all banks idle state.
Once in the Idle state, two AUTO REFRESH cycles must be
performed. Additionally, a LOAD MODE REGISTER command
for the mode register with the reset DLL bit deactivated is
required. Following these requirements, the DDR SDRAM is
ready for NORMAL OPERATION.
March 2002 Rev. 1
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WED3EL7216S
PROGRAMMABLE IOH/IOL
WRITE
The normal full drive strength for all outputs are specified to
be SSTL class 2. The WED3EL7216 supports an option for
reduced drive. This option is intended for the support of
the lighter load and or point-to-point environments. The
command and placement of this device into reduced drive
mode will place the output drive at ~54% of the SSTL-2.
The WRITE command is used to initiate a burst write. Input
data appearing on the DQ’s will be written into the address
location of the array.
PRECHARGE
DESELECT
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a speci-
fied time (tRP) after the PRECHARGE command is issued.
The DESELECT command prevents new commands from
being executed by the WED3EL7216S devices.
NO OPERATION (NOP)
The NOP command is used to instruct the selected DDR
SDRAM device to perform idle or wait states. During these
states, the DDR SDRAM device is unable to register new
commands, operations already in progress are not affected.
LOAD MODE REGISTER
The MODE REGISTERS are loaded via inputs A0-A11. The
LOAD MODE REGISTER command can only be issued when
all DDR SDRAM internal banks are idle.
ACTIVE
The ACTIVE command is used to open (or activate) a row
in a particular bank for a subsequent access. The value on
the BA0, BA1 inputs selects the bank, ant the address pro-
vided on inputs A0-A11 selects the row. The row remains
active for accesses until a PRECHARGE command is issued.
A PRECHARGE command must be issued before opening a
different row in the same bank.
READ
The READ command is used to initiate a BURST READ ac-
cess to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
Ax. Addressed location of the array will drive its contents
onto the DQ’s or the device
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WED3EL7216S
FUNCTIONAL BLOCK DIAGRAM
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WED3EL7216S
PIN CONFIGURATION
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WED3EL7216S
PIN DESCRIPTIONS
BGA LOC ATIONS
F4, F16, G5, G15,
K1, K12, L2, L13,
N6, M8
SYMBOL
CKx, CKx\
DESCRIPTION
G4, G16, K2, K13
M6
CKEx
G1, G13, K4, K16
M12
C Sx\
F4, F16, G5, G15,
K1, K12, L2, L13,
N7, M9
G4, G16, K2, K14
M7
RASx\, C ASx\
WEx\
Clock: CKx and CKx\ are differential clock inputs. All address and
cont rol input signals are sampled on t he crossing of t he posit ive
edge o f CKx and negat ive edge of CKx\. Out put dat a ( DQ’ s and
DQS) is referenced to the crossings of the differential clock inputs
Clock Enable: CKE cont rols t he clock input s. CKE high enables,
CKE Low disables the clock input pins. Driving CKE Low pro-vides
PRECHARGE POWER-DOWN and SELF REFRESH
operations, or ACTIVE POWER-DOWN. CKE is synchronous
for POWER-DOWN ent ry and exit , and for SELF REFRESH ent ry
CKE is Asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read and
writ e accesses. Input buffers are disabled during POWER-DOWN
Input buffers are disabled during SELF REFRESH. CKE is an
SSTL-2 input but will det ect an LVCMOS LOW level aft er VCC
is applied
Chip Select: CSx\ enagles t he COMMAND regist er(s) of each of
t he five (5) cont ained words. All commands are masked when CSx\
is registered HIGH. CSx\ provides for external bank selection
on systems with multiple banks. CSx\ is considered part of the
COMMAND CODE.
Command Input s: RASx, CASx, and Wex\ define t he command
being ent ered
Input Data Mask. DM is an input mask signal for write data.
Input dat a is masked when DQMLx or Hx is sampled HIGH at
t ime of a WRITE access. DM is sampled on bot h edges of DQSLx
and DQSHx
Bank Address Inputs: BA0, BA1 define which bank an ACTIVE
READ, WRITE, or PRECHARGE command is being applied
Address Input : Provide the row address for Active commands, and
t he column address and aut o precharge bit (A10) for READ/WRITE
commands to select one location out of the memory array int the
respective bank. A10 sampled during a PRECHARGE command
det ermines whether t he PRECHARGE applies t o one bank or
all banks. T he address input s also provide t he op-code during
a MODE RESI ST ER SE T c o mma n d.
DQMLx, DQMHx
E8, E9
BA0, BA1
A7, A8, A9, A10, B7
B8, B9, B10, C7, C8
C9, C10, D7
A0-A11, A12
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