WED9LC6416V
128Kx32 SSRAM/4Mx32 SDRAM
FEATURES
s
Clock speeds:
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
s
DSP Memory Solution
• Texas Instruments TMS320C6201
• Texas Instruments TMS320C6701
s
Packaging:
• 153 pin BGA, JEDEC MO-163
s
3.3V Operating supply voltage
s
Direct control interface to both the SSRAM and SDRAM ports
on the “C6x”
s
Common address and databus
s
65% space savings vs. monolithic solution
s
Reduced system inductance and capacitance
Advanced*
External Memory Solution for Texas Instruments TMS320C6000 DSP
DESCRIPTION
The WED9LC6416VxxBC is a 3.3V, 128K x 32 Synchronous
Pipeline SRAM and a 4Mx32 Synchronous DRAM array con-
structed with one 128K x 32 SBSRAM and two 4Mx16 SDRAM die
mounted on a multilayer laminate substrate. The device is
packaged in a 153 lead, 14mm by 22mm, BGA.
The WED9LC6416VxxBC provides a total memory solution for the
Texas Instruments TMS320C6201 and the TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock speeds
of 200, 166,150, and 133 MHz, allowing the user to develop a fast
external memory for the SSRAM interface port .
The SDRAM is available in clock speeds of 125 and 100 MHz,
allowing the user to develop a fast external memory for the
SDRAM interface port .
The WED9LC6416V is available in both commercial and industrial
temperature ranges.
* This data sheet describes a product that may or may not be under development and
is subject to change or cancellation without notice.
FIG. 1
1
A
B
C
D
E
F
G
H
J
L
M
N
P
R
T
U
PIN CONFIGURATION
TOP VIEW
2
DQ
23
DQ
22
V
CCQ
DQ
21
DQ
20
V
CCQ
NC
NC
A
7
NC
V
CCQ
DQ
11
DQ
10
V
CCQ
DQ
9
DQ
8
2
3
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
NC
A
8
A
9
NC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
3
4
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
BWE
2
BWE
0
V
SS
V
SS
V
SS
SSOE
4
5
V
SS
SDCE
V
SS
SDCLK
V
SS
V
SS
V
SS
V
SS
BWE
3
BWE
1
V
SS
SSCLK
V
SS
SSCE
5
6
V
SS
V
SS
NC
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
NC
NC
V
SS
V
SS
V
SS
NC
NC
6
7
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
A
2
A
1
A
0
NC
NC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
7
8
DQ
24
DQ
25
V
CCQ
DQ
26
DQ
27
V
CCQ
A
4
A
3
A
11
A
13
A
15
V
CCQ
DQ
4
DQ
5
V
CCQ
DQ
6
DQ
7
8
9
DQ
28
DQ
29
V
CCQ
DQ
30
DQ
31
V
CCQ
A
5
A
10
A
12
A
14
A
16
V
CCQ
DQ
0
DQ
1
V
CCQ
DQ
2
DQ
3
9
V
SS
NC
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
SSCE
SDCE
V
CC
V
CCQ
PIN DESCRIPTION
A
0-16
DQ
0-31
SSCLK
SSADC
SSWE
SSOE
SDCLK
SDRAS
SDCAS
SDWE
SDA
10
BWE
0-3
Address Bus
Data Bus
SSRAM Clock
SSRAM Address Status Control
SSRAM Write Enable
SSRAM Output Enable
SDRAM Clock
SDRAM Row Address Strobe
SDRAM Column Address Strobe
SDRAM Write Enable
SDRAM Address 10/auto precharge
SSRAM Byte Write Enables
SDRAM SDQM 0 - 3
Chip Enable SSRAM Device
Chip Enable SDRAM Device
Power Supply pins, 3.3V
Data Bus Power Supply pins,
3.3V (2.5V future)
Ground
No Connect
DQ
19
DQ
18
V
CCQ
DQ
17
DQ
16
V
CCQ
NC
NC
A
6
NC
V
CCQ
DQ
12
DQ
13
V
CCQ
DQ
14
DQ
15
1
SDWE SDA
10
SDRAS SDCAS
K
NC / A
17
NC / A
18
NC / A
19
SSADC SSWE
January 20001
1
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WED9LC6416V
FIG. 2
BLOCK DIAGRAM
A
0-16
A
0
A
1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BWE
BW
1
BW
2
BW
3
BW
4
CE
2
OE
ADSC
CLK
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A
10
/AP
BA
0
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A
11
A
10
/AP
BA
0
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
DQ
1-8
DQ
9-16
DQ
17-24
DQ
25-32
DQ
0-7
DQ
8-15
DQ
16-23
DQ
24-31
SSWE
BWE
0
BWE
1
BWE
2
BWE
3
SSCE
SSOE
SSADC
SSCLK
DQ
0-31
DQ
0-7
DQ
8-15
DQ
0-7
DQ
8-15
SDA
10
A
12
A
13
SDCE
SDRAS
SDCAS
SDWE
SDCLK
DQ
0-7
DQ
8-15
DQ
16-23
DQ
24-31
A
12
A
13
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January 2001
WED9LC6416V
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol
SSCLK
SSADS
SSOE
SSWE
SSCE
SDCLK
SDCE
SDRAS
SDCAS
SDWE
Type
Input
Input
Input
Input
Input
Input
Signal
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Polarity
Function
Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
Active Low
Active Low
Active Low
Active Low
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
to be executed by the SSRAM.
SSCE disable or enable SSRAM device operation.
SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE
0-3
.
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation
to be executed by the SDRAM.
Address bus for SSRAM and SDRAM
A
0
and A
1
are the burst address inputs for the SSRAM
During a Bank Active command cycle, A
0-11
, SDA
10
defines the row address (RA
0-10
) when sampled at the
rising clock edge.
Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
A
0-16
,
SDA
10
Input
Level
—
During a Read or Write command cycle, A
0-7
defines the column address (CA
0-7
) when sampled at the
rising clock edge. In addition to the row address, SDA
10
is used to invoke Autoprecharge operation at the
end of the Burst Read or Write Cycle. If SDA
10
is high, autoprecharge is selected and A
12
and A
13
define
the bank to be precharged. If SDA
10
is low, autoprecharge is disabled.
During a Precharge command cycle, SDA
10
is used in conjunction with A
12
and A
13
to control which bank(s)
to precharge. If SDA
10
is high, all banks will be precharged regardless of the state of A
12
and A
13
. If
SDA
10
is low, then A
12
and A
13
are used to define which bank to precharge.
DQ
0-31
BWE
0-3
Input
Output
Input
Level
Pulse
—
Data Input/Output are multiplexed on the same pins.
BWE
0-3
perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE
0
is associated with DQ
0-7
, BWE
1
with DQ
8-15
, BWE
2
with DQ
16-23
and BWE
3
with DQ
24-31
.
Power and ground for the input buffers and the core logic.
Data base power supply pins, 3.3V (2.5V future).
Vcc, Vss
V
CCQ
Supply
Supply
January 20001
3
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
WED9LC6416V
ABSOLUTE MAXIMUM RATINGS
Voltage on Vcc Relative to Vss
Vin (DQx)
Storage Temperature (BGA)
Junction Temperature
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to Vcc +0.5V
-55°C to +125°C
+175°C
100 mA
RECOMMENDED DC OPERATING CONDITIONS
(V
CC
= 3.3V -5% / +10% unless otherwise noted;
0°C
≤
T
A
≤
70°C, Commercial; -40°C
≤
T
A
≤
85°C, Industrial)
Parameter
Supply Voltage (1)
Input High Voltage (1,2)
Input Low Voltage (1,2)
Input Leakage Current
0
≤
V
IN
≤
Vcc
Output Leakage (Output Disabled)
0
≤
V
IN
≤
Vcc
Output High (I
OH
= -4mA) (1)
Output Low (I
OL
= 8mA) (1)
Symbol
V
CC
V
IH
V
IL
IL
I
ILo
V
OH
V
OL
Min
3.135
2.0
-0.3
-10
-10
2.4
—
Max
3.6
V
CC
+0.3
0.8
10
10
—
0.4
Units
V
V
V
µA
µA
V
V
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in operational
sections of this specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: V
IH
≤
+6.0V for t
≤
t
KC
/2
Underershoot: V
IL
≥
-2.0V for t
≤
t
KC
/2
(V
CC
= 3.3V -5% / +10% unless otherwise noted; 0°C
≤
T
A
≤
70°C, Commercial; -40°C
≤
T
A
≤
85°C, Industrial)
Description
Power Supply Current:
Operating (1,2,3)
Conditions
Symbol
Frequency
133MHz
150MHz
166MHz
200MHz
133MHz
150MHz
166MHz
200MHz
83MHz
100MHz
125MHz
Typ
400
450
500
550
300
350
400
450
220
235
255
20.0
Max
550
580
625
700
450
480
525
585
240
250
280
40.0
Units
DC ELECTRICAL CHARACTERISTICS
SSRAM Active / DRAM Auto Refresh
Icc
1
mA
Power Supply Current
Operating (1,2,3)
SSRAM Active / DRAM Idle
Icc
2
mA
Power Supply Current
Operating (1,2,3)
SDRAM Active / SSRAM Idle
SSCE and SDCE
≤
Vcc -0.2V,
All other inputs at Vss +0.2
≤
V
IN
or
V
IN
≤
V
CC
-0.2V, Clk frequency = 0
SSCE and SDCE
≤
V
IH
min
All other inputs at V
IL
max
≤
V
IN
or
V
IN
≤
V
CC
-0.2V, Clk frequency = 0
Icc
3
mA
CMOS Standby
I
SB1
mA
TTL Standby
Auto Refresh
I
SB2
Icc
5
30.0
190
55.0
250
mA
mA
NOTES:
1. I
CC
(operating) is specified with no output current. I
CC
(operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE
≥
V
IH
) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. I
CC
(operating) is specified at specified frequency.
BGA CAPACITANCE
Description
Address Input Capacitance (1)
Input/Output Capacitance (DQ) (1)
Control Input Capacitance (1)
Clock Input Capacitance (1)
NOTE:
1. This parameter is sampled.
Conditions
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
T
A
= 25°C; f = 1MHz
Symbol
C
I
C
O
C
A
C
CK
Typ
5
8
5
4
Max
8
10
8
6
Units
pF
pF
pF
pF
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
January 2001
WED9LC6416V
(V
CC
= 3.3V -5% / +10% unless otherwise noted; 0°C
≤
T
A
≤
70°C, Commercial; -40°C
≤
T
A
≤
85°C, Industrial)
Symbol
Parameter
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Clock to output valid
Clock to output invalid
Clock to output on Low-Z
Clock to output in High-Z
Output Enable to output valid
Output Enable to output in Low-Z
Output Enable to output in High-Z
Address, Control, Data-in Setup Time to Clock
Address, Control, Data-in Hold Time to Clock
t
KHKH
t
KLKH
t
KHKL
t
KHQV
t
KHQX
t
KQLZ
t
KQHZ
t
OELQV
t
OELZ
t
OEHZ
t
S
t
H
200MHz
Min
Max
5
1.6
1.6
2.5
1.5
0
1.5
3
2.5
0
3.0
1.5
0.5
166MHz
Min
Max
6
2.4
2.4
3.5
1.5
0
1.5
3.5
3.5
0
3.5
1.5
0.5
150MHz
Min
Max
7
2.6
2.6
3.8
1.5
0
1.5
3.8
3.8
0
3.5
1.5
0.5
133MHz
Min
Max
8
2.8
2.8
4.0
1.5
0
1.5
4.0
4.0
0
3.8
1.5
0.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSRAM AC CHARACTERISTICS
January 20001
5
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