White Electronic Designs
2Mx32 5V Flash Module
FEATURES
Access Time of 90, 120, 150ns
Packaging:
• 66 pin, PGA Type, 1.185" square, Hermetic
Ceramic HIP (Package 401).
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880")
square (Package 510) 3.56mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (FIGURE 3)
Sector Architecture
• 32 equal size sectors of 64KBytes per each 2Mx8
chip
• Any combination of sectors can be erased. Also
supports full chip erase.
Minimum 100,000 Write/Erase Cycles Minimum
Organized as 2Mx32
WF2M32-XXX5
Commercial, Industrial, and Military
Temperature Ranges
5 Volt Read and Write. 5V ± 10% Supply.
Low Power CMOS
Data# Polling and Toggle Bit feature for detection of
program or erase cycle completion.
Supports reading or programming data to a sector
not being erased.
RESET# pin resets internal state machine to the
read mode.
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation, Separate Power and
Ground Planes to improve noise immunity
* This product is subject to change without notice.
Note: For programming information refer to Flash Programming 16M5 Application Note.
FIGURE 1 – PIN CONFIGURATION FOR WF2M32-XHX5
Top View
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
22
12
WE
2#
CS
2#
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1#
A
19
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
A
17
WE
1#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
7
A
12
A
20
A
13
A
8
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4#
WE
4#
I/O
27
A
4
A
5
A
6
WE
3#
CS
3#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
OE#
A
0
-
20
Pin Description
56
I/O0-31
A0-20
WE1-4#
CS1-4#
OE#
VCC
GND
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Block Diagram
WE1# CS1#
WE2# CS2#
WE3# CS3#
WE4# CS4#
A
3
2M x 8
2M x 8
2M x 8
2M x 8
I/O
23
I/O
22
I/O
21
I/O
20
66
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
RESET# internally tied to V
CC
in the HIP package for this pin con-
figuration. See Alternate Pin Configuration with RESET# tied to pin
12 for system control of reset (FIGURE 10, page 11).
October 2004
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WF2M32-XXX5
FIGURE 2 – PIN CONFIGURATION FOR WF2M32-XG2UX5
Top View
RESET#
A0
A1
A2
A3
A4
A5
CS3#
GND
CS4#
WE1#
A6
A7
A8
A9
A10
V
CC
Pin Description
I/O0-31
A0-20
WE1-4#
CS1-4#
OE#
VCC
GND
RESET#
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Reset
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
Block Diagram
WE1# CS1#
RESET#
OE#
A
0-20
2M x 8
2M x 8
WE2# CS2#
WE3# CS3#
WE4# CS4#
V
CC
A11
A12
A13
A14
A15
A16
CS1#
OE#
CS2#
A17
WE2#
WE3#
WE4#
A18
A19
A20
2M x 8
2M x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
The WEDC 68 lead G2U CQFP fills the same fit and function as the
JEDEC 68 lead CQFJ or 68 PLCC. But the G2U has the TCE and lead
inspection advantage of the CQFP form.
0.940"
October 2004
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Short Circuit Output Current
Endurance – Write/Erase Cycles
(Extended Temp)
Data Retention
Symbol
V
T
P
T
T
stg
I
OS
Ratings
-2.0 to +7.0
8
-65 to +125
100
100,000 min
20
Unit
V
W
°C
mA
cycles
years
WF2M32-XXX5
CAPACITANCE
T
A
= +25°C, f = 1.0MHz
Parameter
OE# capacitance
WE1-4# capacitance
HIP (PGA)
HIP (Alternate pinout)
CQFP G4T
CQFP G2U
G2U (Alternate pinout)
CS1-4# capacitance
Data I/O capacitance
Address input capacitance
Symbol
COE
CWE
CWE
CWE
CWE
CWE
CCS
CI/O
CAD
Max
50
20
50
50
20
50
20
20
50
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
Symbol Min
V
CC
V
SS
V
IH
V
IL
T
A
T
A
4.5
0
2.0
-0.5
-55
-40
Typ
5.0
0
-
-
-
-
Max
5.5
0
V
CC
+ 0.5
+0.8
+125
+85
Unit
V
V
V
V
°C
°C
DC CHARACTERISTICS – CMOS COMPATIBLE
V
CC
= 5.0V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Symbol
I
LI
I
LOx32
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz
CS# = V
IL
, OE# = V
IH
V
CC
= 5.5, CS# = V
IH
, f = 5MHz, RESET# = V
CC
± 0.3V
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
Min
Max
10
10
160
240
8.0
0.45
4.2
Unit
µA
µA
mA
mA
mA
V
V
V
0.85xV
CC
3.2
NOTES:
1. The I
CC
current listed includes both the DC operating current and the frequency
dependent component (@ 5MHz). The frequency component typically is less than
2mA/MHz, with OE# at V
IH
.
2. I
CC
active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
October 2004
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
V
CC
= 5.0V, -55°C ≤ T
A
≤ +125°C
Parameter
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
V
CC
Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET# Pulse Width (5)
Symbol
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
Min
90
0
45
0
45
0
45
20
-90
Max
Min
120
0
50
0
50
0
50
20
-120
Max
WF2M32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS - WE# CONTROLLED
-150
Min
150
0
50
0
50
0
50
20
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
µs
sec
sec
ns
ns
Unit
300
15
0
50
44
256
t
OEH
t
RP
10
500
10
500
0
50
300
15
0
50
44
256
10
500
300
15
44
256
NOTES:
1. Typical value for t
WHWH1
is 7µs.
2. Typical value for t
WHWH2
is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5. RESET# internally tied to V
CC
for the default pin configuration in the HIP package.
AC CHARACTERISTICS – READ-ONLY OPERATIONS
V
CC
= 5.0V, -55°C ≤ T
A
≤ +125°C
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS# or OE#
Change, whichever is First
RST Low to Read Mode (1,2)
Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
t
Ready
Min
90
-90
Max
90
90
40
20
20
0
20
0
20
Min
120
-120
Max
120
120
50
30
30
0
20
Min
150
-150
Max
150
150
55
35
35
Unit
ns
ns
ns
ns
ns
ns
ns
µs
NOTES:
1. Guaranteed by design, not tested.
2. RESET# internally tied to V
CC
for the default pin configuration in the HIP package.
October 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
V
CC
= 5.0V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
WF2M32-XXX5
AC CHARACTERISTICS – WRITE/ERASE/PROGRAM OPERATIONS,CS# CONTROLLED
Symbol
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
Min
90
0
45
0
45
0
45
20
-90
Max
Min
120
0
50
0
50
0
50
20
-120
Max
Min
150
0
50
0
50
0
50
20
-150
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
sec
sec
ns
Unit
300
15
0
44
256
t
OEH
10
10
0
300
15
0
44
256
10
300
15
44
256
FIGURE 3 – AC TEST CIRCUIT
AC TEST CONDITIONS
I
OL
Current Source
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
(Bipolar Supply)
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ½.
VZ is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
FIGURE 4 – RESET TIMING DIAGRAM
RESET#
t
RP
t
Ready
October 2004
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
