White Electronic Designs
FEATURES
n
n
Packaging:
• 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
• 68 lead, 40mm Low Profile CQFP ( Package
502 ), 3.5mm (0.140") height.
• 68 lead, Hermetic CQFP (G2T), 22.4mm
(0.880") square (Package 509) 4.57mm
(0.180") height. Designed to fit JEDEC 68
lead 0.990CQFJ footprint (Fig. 3)
n
Sector Architecture
• 32 equal size sectors of 64KBytes per each
2Mx8 chip
• Any combination of sectors can be erased. Also
supports full chip erase.
n
Minimum 100,000 Write/Erase Cycles Minimum
n
Organized as 4Mx32
WF4M32-XXX5
PRELIMINARY*
4MX32 5V FLASH MODULE, SMD 5962-97612 (pending)
Access Times of 100, 120, 150ns
n
User configurable as 8Mx16 or 16Mx8 in HIP and
G4T packages.
n
Commercial, Industrial, and Military Temperature Ranges
n
5 Volt Read and Write. 5V ± 10% Supply.
n
Low Power CMOS
n
Data Polling and Toggle Bit feature for detection of
program or erase cycle completion.
n
Supports reading or programming data to a sector
not being erased.
n
RESET pin resets internal state machine to the read
mode.
n
Built-in Decoupling Caps and Multiple Ground
Pins for Low Noise Operation, Separate Power
and Ground Planes to improve noise immunity
*This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
Note:
For programming information refer to Flash Programming 16M5 Application Note.
F
IG
. 1
1
I/O
8
I/O
9
I/O
10
A
14
A
16
A
11
A
0
A
18
I/O
0
I/O
1
I/O
2
11
P
IN
C
ONFIGURATION
F
OR
WF4M32-XH2X5
T
OP
V
IEW
12
RESET
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Reset
A
0-21
WE
CS
1-4
OE
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
17
WE
I/O
7
I/O
6
I/O
5
I/O
4
33
I/O
24
I/O
25
I/O
26
A
7
A
12
A
21
A
13
A
8
I/O
16
I/O
17
I/O
18
34
V
CC
CS
4
NC
I/O
27
A
4
A
5
A
6
A20
CS
3
GND
I/O
19
44
45
I/O
31
I/O
30
I/O
29
I/O
28
A
1
A
2
A
3
56
CS
2
GND
I/O
11
A
10
A
9
A
15
V
CC
CS
1
A
19
I/O
3
22
V
CC
GND
RESET
B
LOCK
D
IAGRAM
CS
1
A
21
CS
2
CS
3
CS
4
I/O
23
I/O
22
OE
WE
I/O
21
I/O
20
55
66
A
0-20
RESET
2M x 8
2M x 8
2Mx 8
2M x 8
2M
x 8
2M
x 8
2M
x 8
2M
x 8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
August 2002 Rev. 4
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
F
IG
. 2
P
IN
C
ONFIGURATION
F
OR
WF4M32-XG4TX5
T
OP
V
IEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
WF4M32-XXX5
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-21
WE
CS
1-4
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Reset
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
OE
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
V
CC
RESET
GND
NC
B
LOCK
D
IAGRAM
CS
1
A
21
CS
2
CS
3
CS
4
OE
WE
A
0-20
RESET
2M x 8
2M x 8
2M x 8
2M x 8
BUFFER
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
A
17
A
18
A
19
A
20
RESET
NC
A21
2M
x 8
2M
x 8
2M
x 8
2M
x 8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
F
IG
. 3
P
IN
C
ONFIGURATION
F
OR
WF4M32-XG2TX5
T
OP
V
IEW
RESET
A
0
A
1
A
2
A
3
A
4
A
5
NC
GND
NC
WE
A
6
A
7
A
8
A
9
A
10
V
CC
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-20
WE
Address Inputs
Write Enables
Banks Selects
Output Enable
Power Supply
Ground
Reset
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
CS
1-2
OE
The White 68 lead G2T CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ or
68 PLCC. But the G2T has the
TCE and lead inspection
advantage of the CQFP form.
CS
1
RESET
WE
OE
A
0-20
V
CC
GND
RESET
B
LOCK
D
IAGRAM
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
2M x 8
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
OE
CS
2
A
17
NC
NC
NC
A
18
V
CC
A
19
A
20
8
8
8
8
CS
2
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
Note:
CS1& CS2 are used as bank select
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
White Electronic Designs
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Voltage on Any Pin Relative to V
SS
Power Dissipation
Storage Temperature
Short Circuit Output Current
Endurance - Write/Erase Cycles
(Mil Temp)
Data Retention (Mil Temp)
Symbol
V
T
P
T
Tstg
I
OS
Ratings
-2.0 to +7.0
8
-65 to +125
100
100,000 min
20
Unit
V
W
°C
mA
cycles
years
WF4M32-XXX5
C
APACITANCE
(
P
F)
(TA = +25°C, V
IN
= OV,
F
= 1.0MH
Z
)
Parameter
OE capacitance
WE capacitance
CS capacitance
Data I/O capacitance
Address input capacitance
Symbol
HIP (H2) CQFP (G2T) CQFP( G4T)
C
OE
C
WE
C
CS
C
I/O
C
AD
75
75
20
30
75
75
75
50
30
75
20
20
20
30
20
This parameter is guaranteed by design but not tested.
R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Operating Temperature (Mil.)
Operating Temperature (Ind.)
Symbol
V
CC
V
SS
V
IH
V
IL
T
A
T
A
Min
4.5
0
2.0
-0.5
-55
-40
Typ
5.0
0
-
-
-
-
Max
5.5
0
V
CC
+ 0.5
+0.8
+125
+85
Unit
V
V
V
V
°C
°C
DC C
HARACTERISTICS
- CMOS C
OMPATIBLE
(VCC = 5.0V, GND = 0V, TA = -55°C
TO
+125°C)
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Active Current for Read (1)
V
CC
Active Current for Program
or Erase (2)
V
CC
Standby Current
Output Low Voltage
Output High Voltage
Low V
CC
Lock-Out Voltage
Symbol
I
LI
I
LOx32
I
CC1
I
CC2
I
CC3
V
OL
V
OH
V
LKO
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz
CS = V
IL
, OE = V
IH
V
CC
= 5.5, CS = V
IH
, f = 5MHz, RESET = V
IH
I
OL
= 12.0 mA, V
CC
= 4.5
I
OH
= -2.5 mA, V
CC
= 4.5
0.85 x
Vcc
3.2
4.2
Min
HIP
Max
10
10
320
420
20
0.45
0.85 x
Vcc
3.2
4.2
Min
G2T
Max
10
10
215
295
2.0
0.45
0.85 x
Vcc
3.2
4.2
G4T
Min
Max
10
10
345
445
95
0.45
Unit
µA
µA
mA
mA
mA
V
V
V
NOTES:
1. The Icc current listed includes both the DC operating current and the frequency dependent component (@ 5MHz). The
frequency component typically is less than 2mA/MHz, with OE at V
IH
.
2. Icc active while Embedded Algorithm (program or erase) is in progress.
3. DC test conditions V
IL
= 0.3V, V
IH
= V
CC
- 0.3V
HIP = 66 pin, PGA Type, 1.385" square, Hermetic
Ceramic HIP (Package 402).
G2T = 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880")
square. Designed to fit JEDEC 68 lead 0.990" CQFJ
footprint (Fig. 3) (Package 509)
G4T = 68 lead, 40mm Low Profile CQFP, 3.5mm (0.140")
(Package 502 )
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
Parameter
Write Cycle Time
Chip Select Setup Time
Write Enable Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Write Enable Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase (2)
Read Recovery Time before Write
V
CC
Setup Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
RESET Pulse Width
t
OEH
t
RP
10
500
Symbol
Min
t
AVAV
t
ELWL
t
WLWH
t
AVWL
t
DVWH
t
WHDX
t
WLAX
t
WHWL
t
WHWH1
t
WHWH2
t
GHWL
t
VCS
0
50
44
256
10
500
t
WC
t
CS
t
WP
t
AS
t
DS
t
DH
t
AH
t
WPH
100
0
45
0
45
0
45
20
300
15
0
50
-100
Max
Min
120
0
50
0
50
0
50
20
-120
WF4M32-XXX5
AC C
HARACTERISTICS
F
OR
G2T P
ACKAGE
W
RITE
/E
RASE
/P
ROGRAM
O
PERATIONS
- WE C
ONTROLLED
(VCC = 5.0V, TA = -55°C
TO
+125°C)
-150
Max
Min
150
0
50
0
50
0
50
20
300
15
0
50
44
256
10
500
44
256
300
15
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
µs
sec
sec
ns
ns
Unit
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
AC C
HARACTERISTICS
F
OR
G2T P
ACKAGE
R
EAD
-O
NLY
O
PERATIONS
(VCC = 5.0V, TA = -55°C
TO
+125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select High to Output High Z (1)
Output Enable High to Output High Z (1)
Output Hold from Addresses, CS or OE Change,
whichever is First
RST Low to Read Mode (1)
Symbol
Min
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AXQX
t
RC
t
ACC
t
CE
t
OE
t
DF
t
DF
t
OH
t
Ready
0
20
100
100
100
40
20
20
0
20
-100
Max
Min
120
120
120
50
30
30
0
20
-120
Max
Min
150
150
150
55
35
35
-150
Max
ns
ns
ns
ns
ns
ns
ns
µs
Unit
1. Guaranteed by design, not tested.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4
White Electronic Designs
WF4M32-XXX5
AC C
HARACTERISTICS
F
OR
G2T P
ACKAGE
W
RITE
/E
RASE
/P
ROGRAM
O
PERATIONS
,CS C
ONTROLLED
(VCC = 5.0V, GND = 0V, TA = -55°C
TO
+125°C)
Parameter
Write Cycle Time
Write Enable Setup Time
Chip Select Pulse Width
Address Setup Time
Data Setup Time
Data Hold Time
Address Hold Time
Chip Select Pulse Width High
Duration of Byte Programming Operation (1)
Sector Erase Time (2)
Read Recovery Time
Chip Programming Time
Chip Erase Time (3)
Output Enable Hold Time (4)
t
OEH
10
Symbol
Min
t
AVAV
t
WLEL
t
ELEH
t
AVEL
t
DVEH
t
EHDX
t
ELAX
t
EHEL
t
WHWH1
t
WHWH2
t
GHEL
0
44
256
10
t
WC
t
WS
t
CP
t
AS
t
DS
t
DH
t
AH
t
CPH
100
0
45
0
45
0
45
20
300
15
0
44
256
10
-100
Max
Min
120
0
50
0
50
0
50
20
300
15
0
44
256
-120
Max
Min
150
0
50
0
50
0
50
20
300
15
-150
Max
ns
ns
ns
ns
ns
ns
ns
ns
µs
sec
µs
sec
sec
ns
Unit
NOTES:
1. Typical value for tWHWH1 is 7µs.
2. Typical value for tWHWH2 is 1sec.
3. Typical value for Chip Erase Time is 32sec.
4. For Toggle and Data Polling.
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
