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Hi-Fi and Telephony Dual Codec
FEATURES
DESCRIPTION
The WM8753L is a low power, high quality stereo Codec with
integrated Voice CODEC designed for portable digital
telephony applications such as mobile phone, or headset with
Hi-Fi playback capability.
The device integrates dual interfaces to two differentially
connected microphones, and includes drivers for speakers,
headphone and earpiece. External component requirements
are reduced as no separate microphone or headphone
amplifiers are required, and Cap-less connections can be made
to all loads. Advanced on-chip digital signal processing
performs tone control, Bass Boost and automatic level control
for the microphone or line input through the ADC. The two
ADCs may be used to support Voice noise cancellation in a
partnering DSP, or for stereo recording.
The WM8753L Hi-Fi DAC can operate as a master or a slave,
with various master clock frequencies including 12 or 24MHz
for USB devices, 13MHz or 19.2MHz for cellular systems, or
standard 256f
s
rates like 12.288MHz and 24.576MHz. Internal
PLLs generate all required clocks for both Voice and Hi-Fi
converters. If audio system clocks already exist, the PLLs may
be committed to alternative uses.
The WM8753L operates at a nominal supply voltage of 2V,
although the digital core can operate at voltages down to 1.42V
to save power, and the maximum for all supplies is 3.6 Volts.
Different sections of the chip can also be powered down under
software control.
•
•
WM8753L
Hi-Fi DAC:
interfaced over I
2
S type link
Audio sample rates:
8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96
•
DAC SNR 98dB, THD -84dB (‘A’ weighted @ 48kHz)
•
ADC SNR 95dB, THD -82dB (‘A’ weighted @ 48kHz)
•
On-chip Headphone Driver with cap-less output option
- 40mW output power on 16Ω / 3.3V
- with 16Ω load: SNR 90dB, THD –75dB
- with 10kΩ load: SNR 94dB, THD –90dB
•
On-chip speaker driver with 0.5W into 8R
•
Voice Codec:
interfaced over Voice interface
•
supports sample rates from 8ks/s to 48ks/s
•
ADC and DAC SNR 82dB, THD -74dB
•
Two Differential Microphone Interfaces
- Dual ADCs support noise cancellation in external DSP
- Programmable ALC / Noise Gate
•
Low-noise bias supplied for electret microphones
Other features
•
On-chip PLLs supporting 12, 13, 19.2MHz and other clocks
•
Cap-less connection options to headphones, earpiece, spkr.
•
Low power, low voltage
- 1.8V to 3.6V (digital core: 1.42V to 3.6V)
- power consumption <20mW all-on with 2V supplies
- <12mW for PCM CODEC operation
•
7x7x0.9mm QFN package, 5x5x0.9mm BGA package
APPLICATIONS
•
•
MP3 Player / Recorder mobile phone
Bluetooth stereo headset
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Advanced Information, June 2004, Rev 3.1
Copyright
2004
Wolfson Microelectronics plc
Advanced Information
WM8753L
TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1
FEATURES ............................................................................................................1
APPLICATIONS .....................................................................................................1
TABLE OF CONTENTS .........................................................................................2
PIN CONFIGURATION - QFN................................................................................4
PIN CONFIGURATION - BGA ...............................................................................4
ORDERING INFORMATION ..................................................................................4
PIN DESCRIPTION ................................................................................................5
ABSOLUTE MAXIMUM RATINGS.........................................................................6
SIMULATED THERMAL PROPERTIES......................................................................... 6
RECOMMENDED OPERATING CONDITIONS .....................................................6
ELECTRICAL CHARACTERISTICS ......................................................................7
TERMINOLOGY ............................................................................................................ 9
OUTPUT PGA’S LINEARITY ....................................................................................... 10
SIGNAL TIMING REQUIREMENTS .....................................................................13
SYSTEM CLOCK TIMING ........................................................................................... 13
MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING .............................. 13
AUDIO INTERFACE TIMING – MASTER MODE......................................................... 14
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 15
CONTROL INTERFACE TIMING – 3-WIRE MODE ..................................................... 16
CONTROL INTERFACE TIMING – 2-WIRE MODE ..................................................... 17
DEVICE DESCRIPTION .......................................................................................18
INTRODUCTION ......................................................................................................... 18
INPUT SIGNAL PATH.................................................................................................. 20
MICROPHONE INPUTS ............................................................................................. 24
PGA CONTROL........................................................................................................... 28
AUTOMATIC LEVEL CONTROL (ALC) ....................................................................... 31
3D STEREO ENHANCEMENT .................................................................................... 34
OUTPUT SIGNAL PATH.............................................................................................. 36
ANALOGUE OUTPUTS ............................................................................................... 42
HEADPHONE SWITCH ............................................................................................... 46
HEADPHONE OUTPUT............................................................................................... 47
INTERRUPT CONTROLLER ....................................................................................... 48
GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 51
DIGITAL AUDIO INTERFACES ................................................................................... 53
AUDIO INTERFACES CONTROL................................................................................ 57
CONTROL INTERFACE .............................................................................................. 61
MASTER CLOCK AND PHASE LOCKED LOOP ......................................................... 65
AUDIO SAMPLE RATES ............................................................................................. 68
POWER SUPPLIES ..................................................................................................... 70
POWER MANAGEMENT............................................................................................. 71
REGISTER MAP.......................................................................................................... 74
TERMINOLOGY .......................................................................................................... 77
DAC FILTER RESPONSES .................................................................................78
ADC FILTER RESPONSES .................................................................................79
VOICE FILTER RESPONSES..............................................................................81
VOICE DAC FILTER RESPONSES ............................................................................. 81
VOICE ADC FILTER RESPONSES ............................................................................. 81
DE-EMPHASIS FILTER RESPONSES ................................................................82
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AI Rev 3.1 June 2004
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WM8753L
Advanced Information
HIGHPASS FILTER..............................................................................................83
PACKAGE DIAGRAM - 48-PIN QFN ...................................................................85
PACKAGE DIAGRAM - 52-PIN BGA...................................................................86
IMPORTANT NOTICE ..........................................................................................87
ADDRESS: .................................................................................................................. 87
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Advanced Information
WM8753L
PIN CONFIGURATION - BGA
PIN CONFIGURATION - QFN
MODE/GPIO3
CSB/GPIO5
MIC2N
MIC1N
GPIO4
VXDIN
SCLK
SDIN
MIC2
MIC1
RXN
48 47 46 45 44 43 42 41 40 39 38 37
VXDOUT
VXCLK
VXFS
LRC
BCLK
ADCDAT
DACDAT
MCLK
DBVDD
DCVDD
DGND
PCMCLK
1
2
3
4
5
6
36
35
34
33
32
31
LINE2
LINE1
ACOP
ACIN
MICBIAS
VMID
VREF
AGND
AVDD
MONO1
MONO2
SPKRVDD
WM8753LEFL
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
GP1/CLK1
LOUT1
GP2/CLK2
HPVDD
ROUT1
HP/SPKRGND
ROUT2
LOUT2
PGND
PVDD
OUT4
OUT3
30
29
28
27
26
25
ORDERING INFORMATION
ORDER CODE
WM8753LGEFL/V
WM8753LGEFL/RV
WM8753LEB/V
WM8753LEB/RV
Note:
QFN Reel quantity = 2,200
BGA Reel quantity = 3,500
TEMPERATURE
RANGE
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
-25°C to +85°C
PACKAGE
48-pin QFN (7x7x0.9mm)
(lead free)
48-pin QFN (7x7x0.9mm)
(lead free, tape and reel)
52-pin BGA (5x5x0.9mm)
52-pin BGA (5x5x0.9mm)
(tape and reel)
MOISTURE
SENSITIVITY LEVEL
MSL3
MSL3
MSL3
MSL3
PEAK SOLDERING
TEMPERATURE
260
o
C
260
o
C
240
o
C
240
o
C
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AI Rev 3.1 June 2004
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WM8753L
PIN DESCRIPTION
BGA
J2
H3
J3
H4
J4
J5
H5
J6
H6
J7
H7
J8
J9
G8
H9
G9
F9
E9
E8
D9
D8
C9
B9
A9
A8
B7
B6
A6
A5
B5
A4
B4
A3
B3
A2
A1
B1
C2
C1
D2
D1
E2
E1
F1
F2
G1
H1
J1
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
NAME
VXDOUT
VXCLK
VXFS
LRC
BCLK
ADCDAT
DACDAT
MCLK
DBVDD
DCVDD
DGND
PCMCLK
GP2/CLK2
GP1/CLK1
PGND
PVDD
HPVDD
OUT4
OUT3
ROUT1
LOUT1
HP/SPKRGND
ROUT2
LOUT2
SPKRVDD
MONO2
MONO1
AVDD
AGND
VREF
VMID
MICBIAS
ACIN
ACOP
LINE1
LINE2
RXP
RXN
MIC1
MIC1N
MIC2
MIC2N
GPIO4
MODE/GPIO3
CSB/GPIO5
SDIN
SCLK
VXDIN
TYPE
Digital Output
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Input/Output
Digital Output
Digital Input
Digital Input
Supply
Supply
Supply
Digital Input
Digital Output
Digital Output
Supply
Supply
Supply
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Analogue Output
Analogue Output
Supply
Analogue Output
Analogue Output
Supply
Supply
Reference
Reference
Analogue Output
Analogue Input
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Digital input/Output
Digital Input / Output
Digital Input / Output
Digital Input / Output
Digital Input
Digital Input
Voice ADC Output
Advanced Information
DESCRIPTION
Voice codec data clock / ADC frame clock
Voice Codec Frame Sync
DAC Frame Sync
DAC data clock input / output
ADC Digital Audio Data Alternative Output
DAC Digital Audio Data Input
Master Clock Input
Digital Buffer Supply (supply for digital I/O buffers)
Digital Core Supply (supply for digital logic, except I/O buffers)
Digital ground (all digital logic)
VOICE codec master clock input (may be looped from PLL output)
General Purpose Output 2, usually PLL2 output
General Purpose Output 1, usually PLL1 output
PLL ground
PLL Supply
Headphone Supply
Analogue Output 4 (Headphone driver)
Analogue Output 3 (Headphone driver)
Headphone Output Right
Headphone Output Left
Headphone and Speaker ground
Speaker Output Right
Speaker Output Left
Speaker Supply
Mono analogue output 2
Mono analogue output 1
Analogue supply (feeds ADC and DAC)
Analogue ground (feeds ADC and DAC)
Buffered ADC and DAC Reference voltage
Decoupling for ADC and DAC reference voltage
Microphone Bias
AC coupled input to ALC PGA in record path
ALC Mix output
Left Channel Input
Right Channel input
RX mono differential input positive signal
RX mono differential input negative signal
Mic Pre-amp input 1
Mic Pre-amp 1 common mode or negative input
Mic Pre-amp input 2
Mic Pre-amp 2 common mode or negative input
GPIO (General Purpose input/output) usually headphone jack insert
autodetect with selectable pull-up/pull-down.
Control interface Mode select on reset or GPIO3
3-wire MPU Chip Select / 2-wire MPU interface address selection or
GPIO5
3-wire MPU Data Input / 2-wire MPU Date Input / Acknowledge
3-wire MPU Clock Input / 2-wire MPU Clock Input
VOICE DAC Input
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AI Rev 3.1 June 2004
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stm32/stm8
