w
DESCRIPTION
The WM8956 is a low power, high quality stereo DAC designed
for portable multimedia applications.
Stereo class D speaker drivers provide 1W per channel into 8Ω
loads with a 5V supply. Low leakage, excellent PSRR and
pop/click suppression mechanisms also allow direct battery
connection to the speaker supply. Flexible speaker boost
settings allow speaker output power to be maximised while
minimising other analogue supply currents.
A highly flexible input configuration for up to three stereo
sources is integrated, with a complete microphone interface.
External component requirements are drastically reduced as no
separate microphone, speaker or headphone amplifiers are
required.
Stereo 24-bit sigma-delta DACs are used with low power over-
sampling digital interpolation filters and a flexible digital audio
interface.
The master clock can be input directly or generated internally by
an onboard PLL, supporting most commonly-used clocking
schemes.
The WM8956 operates at analogue supply voltages down to
2.7V, although the digital supplies can operate at voltages down
to 1.71V to save power. The speaker supply can operate at up
to 5.5V, providing 1W per channel into 8Ω loads. Unused
functions can be disabled using software control to save power.
The WM8956 is supplied in a very small and thin 5x5mm QFN
package, ideal for use in hand-held and portable systems.
WM8956
Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and
Headphone Drivers
FEATURES
•
•
•
•
DAC SNR 99dB (‘A’ weighted), THD -87dB at 48kHz, 3.3V
Pop and click suppression
3D Enhancement
Stereo Class D Speaker Driver
- <0.1% THD with 1W per channel into 8Ω BTL speakers
- 70dB PSRR @217Hz
- 87% efficiency (1W output)
- Flexible internal switching clock
On-chip Headphone Driver
- 40mW output power into 16Ω at 3.3V
- Capless mode support
- THD+N -70dB at 20mW, SNR 99dB with 16Ω load
Microphone Interface
- Pseudo differential for high noise immunity
- Integrated low noise MICBIAS
Low Power Consumption
- 16mW headphone playback (2.7V / 1.8V supplies)
Low Supply Voltages
- Analogue 2.7V to 3.6V (Speaker supply up to 5.5V)
- Digital core and I/O: 1.71V to 3.6V
On-chip PLL provides flexible clocking scheme
Sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1, 48
5x5x0.9mm QFN package
•
•
•
•
•
•
•
APPLICATIONS
•
•
•
Mobile multimedia
Portable media / DVD players
Games consoles
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up
at
http://www.wolfsonmicro.com/enews/
Production Data, January 2009, Rev 4.0
Copyright
©2009
Wolfson Microelectronics plc
WM8956
TABLE OF CONTENTS
Production Data
DESCRIPTION ....................................................................................................... 1
FEATURES............................................................................................................. 1
APPLICATIONS ..................................................................................................... 1
TABLE OF CONTENTS ......................................................................................... 2
PIN CONFIGURATION ........................................................................................... 3
ORDERING INFORMATION .................................................................................. 3
PIN DESCRIPTION ................................................................................................ 4
ABSOLUTE MAXIMUM RATINGS ......................................................................... 5
RECOMMENDED OPERATING CONDITIONS ..................................................... 5
ELECTRICAL CHARACTERISTICS ...................................................................... 6
OUTPUT PGA GAIN............................................................................................... 9
TYPICAL POWER CONSUMPTION .................................................................... 10
SIGNAL TIMING REQUIREMENTS ..................................................................... 11
SYSTEM CLOCK TIMING ............................................................................................ 11
AUDIO INTERFACE TIMING – MASTER MODE ......................................................... 11
AUDIO INTERFACE TIMING – SLAVE MODE ............................................................ 12
CONTROL INTERFACE TIMING – 2-WIRE MODE ..................................................... 13
INTERNAL POWER ON RESET CIRCUIT .......................................................... 14
DEVICE DESCRIPTION ....................................................................................... 16
INTRODUCTION.......................................................................................................... 16
INPUT SIGNAL PATH .................................................................................................. 17
OUTPUT SIGNAL PATH .............................................................................................. 25
ANALOGUE OUTPUTS ............................................................................................... 31
ENABLING THE OUTPUTS ......................................................................................... 34
HEADPHONE OUTPUT ............................................................................................... 35
CLASS D SPEAKER OUTPUTS .................................................................................. 36
VOLUME UPDATES .................................................................................................... 37
HEADPHONE JACK DETECT ..................................................................................... 39
THERMAL SHUTDOWN .............................................................................................. 41
GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 41
DIGITAL AUDIO INTERFACE ...................................................................................... 42
AUDIO INTERFACE CONTROL .................................................................................. 46
CLOCKING AND SAMPLE RATES .............................................................................. 49
CONTROL INTERFACE .............................................................................................. 56
POWER MANAGEMENT ............................................................................................. 56
REGISTER MAP................................................................................................... 59
REGISTER BITS BY ADDRESS .................................................................................. 60
DIGITAL FILTER CHARACTERISTICS ............................................................... 72
DAC FILTER RESPONSES ......................................................................................... 72
DE-EMPHASIS FILTER RESPONSES ........................................................................ 74
APPLICATIONS INFORMATION ......................................................................... 75
RECOMMENDED EXTERNAL COMPONENTS........................................................... 75
PACKAGE DRAWING .......................................................................................... 78
IMPORTANT NOTICE .......................................................................................... 79
ADDRESS: ................................................................................................................... 79
w
PD, January 2009, Rev 4.0
2
Production Data
WM8956
PIN CONFIGURATION
32
31
30
29
28
27
26
25
24
23
22
21
MICBIAS
LINPUT3/JD2
LINPUT2
LINPUT1
RINPUT1
RINPUT2
RINPUT3/JD3
DCVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SPKGND1
SPK_LN
SPK_RP
SPKVDD2
SPKGND2
SPK_RN
SDIN
SCLK
TOP VIEW
20
19
18
17
ORDERING INFORMATION
ORDER CODE
WM8956GEFL/V
WM8956GEFL/RV
Note:
Reel quantity = 3500
TEMPERATURE
RANGE
-40°C to +85°C
-40°C to +85°C
PACKAGE
32-lead QFN (5x5x0.9mm)
(Pb-free)
32-lead QFN (5x5x0.9mm)
(Pb-free, tape and reel)
MOISTURE
SENSITIVITY LEVEL
MSL3
MSL3
PEAK SOLDERING
TEMPERATURE
260°C
260°C
w
PD, January 2009, Rev 4.0
3
WM8956
PIN DESCRIPTION
PIN NO
1
2
NAME
MICBIAS
LINPUT3 / JD2
TYPE
Analogue Output
Analogue Input
Microphone bias
Left channel line input /
Left channel positive differential MIC input /
Jack detect input pin
Left channel line input /
Left channel positive differential MIC input
Left channel single-ended MIC input /
Left channel negative differential MIC input
Right channel single-ended MIC input /
Right channel negative differential MIC input
Right channel line input /
Right channel positive differential MIC input
Right channel line input /
Right channel positive differential MIC input /
Jack detect input pin
Digital core supply
DESCRIPTION
Production Data
3
4
5
6
7
LINPUT2
LINPUT1
RINPUT1
RINPUT2
RINPUT3 / JD3
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Analogue Input
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Note:
1.
2.
DCVDD
DGND
DBVDD
MCLK
BCLK
DACLRC
DACDAT
GPIO1
DNC
SCLK
SDIN
SPK_RN
SPKGND2
SPKVDD2
SPK_RP
SPK_LN
SPKGND1
SPK_LP
SPKVDD1
VMID
AGND
HP_R
OUT3
HP_L
AVDD
GND_PADDLE
Supply
Supply
Supply
Digital Input
Digital Input / Output
Digital Input / Output
Digital Input
Digital Input / Output
Do not connect
Digital Input
Digital Input/Output
Analogue Output
Supply
Supply
Analogue Output
Analogue Output
Supply
Analogue Output
Supply
Analogue Output
Supply
Analogue Output
Analogue Output
Analogue Output
Supply
Digital ground (Return path for both DCVDD and DBVDD)
Digital buffer (I/O) supply
Master clock
Audio interface bit clock
Audio interface DAC left / right clock
DAC digital audio data
GPIO1 pin
Leave this pin floating
Control interface clock input
Control interface data input / 2-wire acknowledge output
Right speaker negative output
Ground for speaker drivers 2
Supply for speaker drivers 2
Right speaker positive output
Left speaker negative output
Ground for speaker drivers 1
Left speaker positive output
Supply for speaker drivers 1
Midrail voltage decoupling capacitor
Analogue ground (Return path for AVDD)
Right output (Line or headphone)
Mono, left, right or buffered midrail output for capless mode
Left output (Line or headphone)
Analogue supply
Die Paddle (Note 1)
It is recommended that the QFN ground paddle should be connected to analogue ground on the application PCB.
Refer to the application note WAN_0118 on “Guidelines on How to Use QFN Packages and Create Associated PCB
Footprints”
w
PD, January 2009, Rev 4.0
4
Production Data
WM8956
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously
operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given
under Electrical Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30°C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30°C / 60% Relative Humidity. Supplied in moisture barrier bag.
The Moisture Sensitivity Level for each package type is specified in Ordering Information.
CONDITION
Supply voltages (excluding SPKVDD1 and SPKVDD2)
SPKVDD1, SPKVDD2
Voltage range digital inputs
Voltage range analogue inputs
Operating temperature range, T
A
Storage temperature after soldering
Notes
1.
2.
3.
4.
5.
Analogue, digital and speaker grounds must always be within 0.3V of each other.
All digital and analogue supplies are completely independent from each other (i.e. not internally connected).
DCVDD must be less than or equal to AVDD and DBVDD.
AVDD must be less than or equal to SPKVDD1 and SPKVDD2.
SPKVDD1 and SPKVDD2 must be high enough to support the peak output voltage when using DCGAIN and ACGAIN
functions, to avoid output waveform clipping. Peak output voltage is AVDD*(DCGAIN+ACGAIN)/2.
MIN
-0.3V
-0.3V
DGND -0.3V
AGND -0.3V
-40°C
-65°C
MAX
+4.5V
+7V
DBVDD +0.3V
AVDD +0.3V
+85°C
+150°C
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supplies range
Speaker supply range
Ground
SYMBOL
DCVDD
DBVDD
AVDD
SPKVDD1, SPKVDD2
DGND, AGND, SPKGND1,
SPKGND2
MIN
1.71
1.71
2.7
2.7
0
TYP
MAX
3.6
3.6
3.6
5.5
UNIT
V
V
V
V
V
w
PD, January 2009, Rev 4.0
5
微控制器 MCU
