White Electronic Designs
WME128K8-XXX
128Kx8 CMOS MONOLITHIC EEPROM, SMD 5962-96796
FEATURES
Read Access Times of 120, 140, 150, 200, 250,
300ns
JEDEC Approved Packages
• 32 pin, Hermetic Ceramic, 0.600" DIP
(Package 300)
• 32 lead, Hermetic Ceramic, 0.400" SOJ
(Package 101)
Commercial, Industrial and Military Temperature
Ranges
MIL-STD-883 Compliant Devices Available
Write Endurance 10,000 Cycles
Data Retention at 25°C, 10 Years
Low Power CMOS Operation
Automatic Page Write Operation
• Internal Address and Data Latches for 128 Bytes
• Internal Control Timer
Page Write Cycle Time 10ms Max.
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
This product is subject to change without notice.
FIGURE 1 –
Pin Configuration
32 DIP
32 CSOJ
Top View
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
Pin Description
A0-16
I/O0-7
CS#
OE#
WE#
V
CC
V
SS
Address Inputs
Data Input/Output
Chip Selects
Output Enable
Write Enable
+5.0v Power
Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
WE#
NC
A14
A13
A8
A9
A11
OE#
A10
CS#
I/O7
I/O6
I/O5
I/O4
I/O3
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
January 2004 Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
Symbol
T
A
T
STG
V
G
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
Unit
°C
°C
V
V
CS#
H
L
L
X
X
X
OE#
X
L
H
H
X
L
WE#
X
H
L
X
H
X
WME128K8-XXX
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Write
Inhibit
Data I/O
High Z
Data Out
Data In
High Z/Data Out
NOTE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
CAPACITANCE
T
A
= +25°C
Parameter
Input Capacitance
Output Capacitance
Symbol
C
IN
C
OUT
Conditions
V
IN
= 0 V, f = 1MHz
V
I/O
= 0 V, f = 1MHz
Max Unit
20 pF
20 pF
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
Symbol
V
CC
V
IH
V
IL
T
A
T
A
Min
4.5
2.0
-0.5
-55
-40
Max
5.5
V
CC
+ 0.3
+0.8
+125
+85
Unit
V
V
V
°C
°C
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 2.1mA, V
CC
= 4.5V
I
OH
= -400µA, V
CC
= 4.5V
Min
Max
10
10
80
0.625
0.45
Unit
µA
µA
mA
mA
V
V
2.4
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
FIGURE 2 –
AC Test Circuit
Current Source
AC TEST CONDITIONS
IOL
D.U.T
Ceff = 50 pf
Vz ~ 1.5V
~
Bipolar Supply
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
Current Source
IOH
Notes: V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
READ
Figure 3 shows Read cycle waveforms. A read cycle begins
with selection address, chip select and output enable. Chip
select is accomplished by placing the CS# line low. Output
enable is done by placing the OE# line low. The memory
places the selected data byte on I/O0 through I/O7 after
the access time. The output of the memory is placed in a
high impedance state shortly after either the OE# line or
CS# line is returned to a high level.
WME128K8-XXX
FIGURE 3 – READ WAVEFORMS
t
RC
ADDRESS
ADDRESS VALID
CS#
t
ACS
OE#
t
ACC
OUTPUT
HIGH Z
t
OE
t
DF
t
OH
OUTPUT
VALID
NOTE:
OE# may be delayed up to t
ACS
- t
OE
after the falling edge of CS#
without impact on t
OE
or by t
ACC
- t
OE
after an address change without impact on t
ACC
.
AC READ CHARACTERISTICS
(See Figure 3)
V
CC
= 5.0V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
Read Cycle Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Address Change, OE# or CS#
Output Enable to Output Valid
Chip Select or OE# to High Z Output
Symbol
t
RC
t
ACC
t
ACS
t
OH
t
OE
t
DF
-120
Min
120
Max
120
120
0
0
50
60
0
0
-140
Min
140
Max
140
140
55
70
0
0
-150
Min
150
Max
150
150
55
70
0
0
-200
Min
200
Max
200
200
55
70
0
0
-250
Min
250
Max
250
250
85
70
0
0
-300
Min
300
Max
300
300
85
70
Unit
ns
ns
ns
ns
ns
ns
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WRITE
Write operations are initiated when both CS# and WE#
are low and OE# is high. The EEPROM devices support
both a CS# and WE# controlled write cycle. The address is
latched by the falling edge of either CS# or WE#, whichever
occurs last.
The data is latched internally by the rising edge of either
CS# or WE#, whichever occurs first. A byte write operation
will automatically continue to completion.
WME128K8-XXX
WRITE CYCLE TIMING
Figures 4 and 5 show the write cycle timing relationships.
A write cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
The WE# line transition from high to low also initiates
an internal 150µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
AC WRITE CHARACTERISTICS
V
CC
= 5.0V, V
SS
= 0V, -55°C ≤ T
A
≤ +125°C
128Kx8
Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
Data Hold Time
Chip Select Hold Time
Data Set-up Time
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
Symbol
Min
t
WC
t
AS
t
WP
t
CS
t
AH
t
DH
t
CH
t
DS
t
OES
t
OEH
t
WPH
10
100
0
100
10
0
50
0
0
50
Max
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WME128K8-XXX
FIGURE 4 – WRITE WAVEFORMS WE# CONTROLLED
t
WC
OE#
t
OES
ADDRESS
t
AS
CS#
t
CS
WE
#
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
FIGURE 5 – WRITE WAVEFORMS CS# CONTROLLED
t
WC
OE#
t
OES
ADDRESS
t
AS
WE
#
t
CS
CS
#
t
WP
t
DS
DATA IN
t
WPH
t
DH
t
AH
t
CSH
t
OEH
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2004
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
