WMS128K8V-XXX
128Kx8 3.3V MONOLITHIC SRAM
FEATURES
s
Access Times 15, 17, 20, 25, 35ns
s
Revolutionary, Center Power/Ground Pinout
JEDEC Approved
• 32 lead Ceramic SOJ (Package 101)
• 32 lead Ceramic Flat Pack (Package 220)**
s
Evolutionary, Corner Power/Ground Pinout
JEDEC Approved
• 32 pin Ceramic DIP (Package 300)
s
32 pin, Rectangular Ceramic Leadless Chip Carrier
(Package 601)
PRELIMINARY*
s
MIL-STD-883 Compliant Devices Available
s
Commercial, Industrial and Military Temperature Range
s
3.3 Volt Power Supply
s
Low Power CMOS
s
TTL Compatible Inputs and Outputs
* This data sheet describes a product under development, not fully
characterized, and is subject to change without notice.
** Package under developement.
REVOLUTIONARY PINOUT
32 CSOJ (DR)
32 FLATPACK (FR)**
EVOLUTIONARY PINOUT
32 DIP (C)
32 CLCC
TOP VIEW
A0
A1
A2
A3
CS
I/O1
I/O2
V
CC
V
SS
I/O3
I/O4
WE
A4
A5
A6
A7
TOP VIEW
A16
A15
A14
A13
OE
I/O8
I/O7
V
SS
V
CC
I/O6
I/O5
A12
A11
A10
A9
A8
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN DESCRIPTION
A
0-16
I/O
0-7
CS
OE
WE
V
CC
V
SS
NC
Address Inputs
Data Input/Outputs
Chip Select
Output Enable
Write Enable
+3.3V Power
Ground
Not Connected
June 2000 Rev. 3
1
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WMS128K8V-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
5.5
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
X
H
L
H
TRUTH TABLE
WE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
T
A
Min
3.0
2.2
-0.3
-55
Max
3.6
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Parameter
Input capacitance
Output capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
IN
C
OUT
Condition
V
IN
= 0V, f = 1.0MHz
V
OUT
= 0V, f = 1.0MHz
Max Unit
20
20
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 3.3V
±0.3V,
V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current (x 32 Mode)
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 3.3, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, V
CC
= 3.3
CS = V
IH
, OE = V
IH
, f = 5MHz, V
CC
= 3.3
I
OL
= 8mA
I
OH
= -4.0mA
2.4
Max
10
10
120
8
0.4
Units
µA
µA
mA
mA
V
V
AC TEST CIRCUIT
I
OL
Current Source
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Typ
V
IL
= 0, V
IH
= 2.5
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
Output Timing Reference Level
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
2
WMS128K8V-XXX
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
1
Symbol
-15
Min
15
15
0
15
10
5
5
8
8
5
5
0
Max
Min
17
-17
Max
-20
Min
20
17
0
17
11
5
5
9
9
10
10
20
12
5
5
20
0
Max
Min
25
-25
Max
-35
Min
35
25
0
25
15
5
5
12
12
15
15
35
20
35
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(V
CC
= 3.3V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
0
Symbol
-15
Min
15
13
13
10
13
0
0
5
8
0
Max
-17
Min
17
14
14
11
14
0
0
5
9
0
Max
Min
20
15
15
12
15
0
0
5
10
0
-20
Max
-25
Min
25
20
20
15
20
0
0
5
10
0
Max
-35
Min
35
30
30
18
30
0
0
5
15
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
WMS128K8V-XXX
TIMING WAVEFORM - READ CYCLE
t
RC
ADDRESS
t
AA
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
WRITE CYCLE - CS CONTROLLED
WS32K32-XHX
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
4
WMS128K8V-XXX
PACKAGE 101:
32 LEAD, CERAMIC SOJ
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 220:
32 LEAD, CERAMIC FLAT PACK
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
5
White Electronic Designs Corporation • Phoenix, AZ • (602) 437-1520
FPGA/CPLD
