White Electronic Designs
WMS256K16-XXX
256Kx16 MONOLITHIC SRAM, SMD 5962-96902
FEATURES
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■
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Access Times 17, 20, 25, 35ns
MIL-STD-883 Compliant Devices Available
Packaging
• 44 pin Ceramic SOJ (Package 102)
• 44 lead Ceramic Flatpack (Package 225)
• 44 lead Formed Ceramic Flatpack
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■
Organized as 256Kx16
Data Byte Control:
• Lower Byte (LB#) = I/O
1-8
• Upper Byte (UB#) = I/O
9-16
■
2V Minimum Data Retention for battery back up
operation (WMS256K16L-XXX Low Power Version
Only)
Commercial, Industrial and Military Temperature
Range
5V Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
V
CC
GND
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
PIN CONFIGURATION FOR WMS256K16-XXX
44 CSOJ
44 FlatpacK
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
GND
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
■
■
■
■
PIN DESCRIPTION
A
0-17
LB#
UB#
I/O
1-16
CS#
OE#
WE#
V
CC
GND
NC
Address Inputs
Lower-Byte Control (I/O
1-8
)
Upper-Byte Control (I/O
9-16
)
Data Input/Output
Chip Select
Output Enable
Write Enable
+5.0V Power
Ground
No Connection
August 2004
Rev. 6
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
TRUTH TABLE
CS#
H
L
L
L
WE#
X
H
X
H
OE#
X
H
X
L
LB#
X
X
H
L
H
L
L
H
L
UB#
X
X
H
H
L
L
H
L
L
Mode
Not Select
Output Disable
WMS256K16-XXX
Data I/O
I/O
1-8
High Z
High Z
Data Out
High Z
Data Out
Data In
High Z
Data In
I/O
9-16
High Z
High Z
High Z
Data Out
Data Out
High Z
Data In
Data In
Power
Standby
Active
Read
Active
L
L
X
Write
Active
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
VG
TJ
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
V
CC
+0.5
150
7.0
Unit
°C
°C
V
°C
V
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.3
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
CAPACITANCE
T
A
= +25°C
Parameter
Input capacitance
Output capacitance
Symbol
C
IN
C
OUT
Condition
V
IN
= 0V, f = 1.0MHz
V
OUT
= 0V, f = 1.0MHz
Max
20
20
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
CS# = V
IH
, OE# = V
IH
, f = 5MHz, V
CC
= 5.5
I
OL
= 6mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
2.4
Min
Max
10
10
275
17
0.4
Units
µA
µA
mA
mA
V
V
NOTE: DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
LOW POWER DATA RETENTION CHARACTERISTICS (WMS256K16L-XXX ONLY)
-55°C ≤ T
A
≤ +125°C
Parameter
Data Retention Supply Voltage
Data Retention Current
August 2004
Rev. 6
Symbol
VDR
I
CCDR
1
Conditions
CS# ≥ V
CC
-0.2V
V
CC
= 3V
2
Min
2.0
Typ
1.0
Max
5.5
8.0
Units
V
mA
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Symbol
Read Cycle
Read Cycle Time
t
RC
Address Access Time
t
AA
Output Hold from Address Change
t
OH
Chip Select Access Time
t
ACS
Output Enable to Output Valid
t
OE
Chip Select to Output in Low Z
t
CLZ
1
Output Enable to Output in Low Z
t
OLZ
1
Chip Disable to Output in High Z
t
CHZ
1
Output Disable to Output in High Z
t
OHZ
1
LB#, UB# Access Time
t
BA
LB#, UB# Enable to Low Z Output
t
BLZ
1
LB#, UB# Disable to High Z Output
t
BHZ
1
1. This parameter is guaranteed by design but not tested.
-17
Min
17
0
17
10
2
0
9
9
10
0
9
0
10
5
0
10
10
12
0
Max
17
0
20
12
5
0
Min
20
-20
Max
20
0
Min
25
WMS256K16-XXX
-25
Max
25
0
25
15
5
0
12
12
14
0
12
Min
35
-35
Max
35
35
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
17
15
AC CHARACTERISTICS
V
CC
= 5.0V, GND = 0V, -55°C ≤ T
A
≤ +125°C
Parameter
Write Cycle
Symbol
-17
Min
17
14
14
10
14
0
2
0
0
14
Max
Min
20
17
17
12
17
0
2
0
0
17
-20
Max
Min
25
20
20
15
20
0
2
0
0
20
-25
Max
Min
35
25
25
20
25
0
2
0
0
25
-35
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
t
WC
Chip Select to End of Write
t
CW
Address Valid to End of Write
t
AW
Data Valid to End of Write
t
DW
Write Pulse Width
t
WP
Address Setup Time
t
AS
Address Hold Time
t
AH
Output Active from End of Write
t
OW
1
Write Enable to Output in High Z
t
WHZ
1
Data Hold Time
t
DH
LB#, UB# Valid to End of Write
t
BW
1. This parameter is guaranteed by design but not tested.
9
10
10
15
AC TEST CIRCUIT
Parameter
I
OL
Current Source
AC TEST CONDITIONS
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
(Bipolar Supply)
I
OH
Current Source
Notes:
Vz is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 Ω.
Vz is typically the midpoint of V
OH
and V
OL
.
I
OL
& IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
August 2004
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
TIMING WAVEFORM - READ CYCLE
t
RC
ADDRESS
t
AA
CS#
ADDRESS
WMS256K16-XXX
t
RC
t
AA
t
OH
t
ACS
t
CHZ
DATA I/O
PREVIOUS DATA VALID
DATA VALID
LB#, UB#
t
BA
t
BLZ
t
CLZ
OE#
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
READ CYCLE 2 (WE# = V
IH
)
DATA VALID
t
OHZ
t
BHZ
READ CYCLE 1 (CS# = OE# = V
IL
, UB# or LB# = V
IL
, WE# = V
IH
)
WRITE CYCLE - WE# CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS#
t
AH
t
BW
LB#, UB#
t
AS
WE#
t
WP
t
OW
t
WHZ
t
DW
DATA VALID
t
DH
DATA I/O
WRITE CYCLE 1, WE# CONTROLLED
WRITE CYCLE - CS# CONTROLLED
t
WC
ADDRESS
WRITE CYCLE - LB#, UB# CONTROLLED
t
WC
ADDRESS
t
AS
CS#
t
AW
t
CW
t
BW
t
AH
CS#
t
AS
t
AW
t
CW
t
BW
t
AH
LB#, UB#
LB#, UB#
t
WP
WE#
WE#
t
WP
t
DW
t
DH
DATA I/O
t
DW
DATA VALID
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 2, CS# CONTROLLED
WRITE CYCLE 3, LB#, UB# CONTROLLED
August 2004
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PACKAGE 102: 44 LEAD, CERAMIC SOJ
WMS256K16-XXX
28.70 (1.13) ± 0.25 (0.010)
0.2 (0.008)
± 0.05 (0.002)
3.96 (0.156) MAX
0.89 (0.035)
Radius TYP
11.3 (0.446)
± 0.2 (0.009)
9.55 (0.376) ± 0.25 (0.010)
1.27 (0.050) ± 0.25 (0.010)
1.27 (0.050) TYP
26.7 (1.050) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
PACKAGE 225: 44 LEAD, CERAMIC FLAT PACK
28.45 (1.120)
±
0.26 (0.010)
2.60 (0.102)
MAX
12.95 (0.510)
±
0.13 (0.005)
10.16 (0.400)
±
0.51 (0.020)
0.43 (0.017)
±
0.05 (0.002)
26.67 (1.050) TYP
0.14 (0.006)
±
0.05 (0.002)
1.27 (0.050) TYP
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
August 2004
Rev. 6
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
