White Electronic Designs
FEATURES
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WS128K32-XXX
128Kx32 SRAM MODULE, SMD 5962-93187 & 5962-95595
Access Times of 15, 17, 20, 25, 35, 45, 55ns
MIL-STD-883 Compliant Devices Available
Packaging
66 pin, PGA Type, 1.075" square, Hermetic Ce
ramic HIP (Package 400)
68 lead, 40mm CQFP (G4T)
1
, 3.56mm (0.140")
(Package 502)
68 lead, 22.4mm CQFP (G2U), 3.56mm (0.140"),
(Package 510)
68 lead, 22.4mm (0.880") square, CQFP (G2L),
5.08mm (0.200") high, (Package 528).
68 lead, 23.9mm Low Profile CQFP (G1U)
1
,
3.57mm (0.140"), (Package 519)
68 lead, 23.9mm Low Profile CQFP (G1T), 4.06
mm (0.160"), (Package 524)
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Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Commercial, Industrial and Military Temperature
Ranges
5 Volt Power Supply
TTL Compatible Inputs and Outputs
Built in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight:
WS128K32-XG1UX
1
- 5 grams typical
WS128K32-XG1TX - 5 grams typical
WS128K32-XG2UX - 8 grams typical
WS128K32-XG2LX - 8 grams typical
WS128K32-XH1X - 13 grams typical
WS128K32-XG4TX
1
- 20 grams typical
All devices are upgradeable to 512Kx32
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Low Power CMOS
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Note 1: Package Not Recommended For New Design
FIG. 1
P
IN
C
ONFIGURATION
F
OR
WS128K32N-XH1X
T
OP
V
IEW
P
IN
D
ESCRIPTION
I/O
0-31
Data Inputs/Outputs
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
May 2003 Rev. 12
1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
FIG. 2
P
IN
C
ONFIGURATION
F
OR
WS128K32-XG4TX
1
T
OP
V
IEW
WS128K32-XXX
P
IN
D
ESCRIPTION
I/O
0-31
A
0-16
WE
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
Note 1: Package Not Recommended For New Design
FIG. 3
P
IN
C
ONFIGURATION
F
OR
WS128K32-XG2UX, WS128K32-XG2LX, WS128K32-XG1TX
AND
WS128K32-XG1UX
1
T
OP
V
IEW
P
IN
D
ESCRIPTION
I/O
0-31
A
0-16
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
B
LOCK
D
IAGRAM
Note 1: Package Not Recommended For New Design
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
2
White Electronic Designs
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
7.0
Unit
°C
°C
V
°C
V
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA) H1
CQFP G4T
CQFP G2U/G2L
CQFP G1U/G1T
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
WS128K32-XXX
T
RUTH
T
ABLE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
R
ECOMMENDED
O
PERATING
C
ONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.3
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
C
APACITANCE
(TA = +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0V, f = 1.0 MHz
V
IN
= 0V, f = 1.0 MHz
20
50
20
20
C
CS
C
I/O
C
AD
V
IN
= 0V, f = 1.0 MHz
V
I/O
= 0V, f = 1.0 MHz
V
IN
= 0V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC C
HARACTERISTICS
(VCC = 5.0V, GND = 0V, TA = -55°C
TO
+125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
V
OH
Sym
I
LI
I
LO
I
CC
I
SB
V
OL
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 8mA, V
CC
= 4.5
I
OH
= -4.0mA, V
CC
= 4.5
Conditions
V
CC
= 5.5, V
IN
= GND to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 2.1mA, V
CC
= 4.5
2.4
2.4
Min
-15
Max
10
10
600
80
0.4
2.4
-35
Min
-17
Max
10
10
600
80
0.4
2.4
-45
Min
-20
Max
10
10
600
80
0.4
2.4
-55
Min
-25
Max
10
10
600
60
0.4
Units
µA
µA
mA
mA
V
V
Units
µA
µA
mA
mA
V
V
Min
Max
10
10
600
60
0.4
Min
Max
10
10
600
60
0.4
Min
Max
10
10
600
60
0.4
I
OH
= -1.0mA, V
CC
= 4.5
Output High Voltage
V
OH
NOTE:
DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
2.4
2.4
D
ATA RETENTION
C
HARACTERISTICS
(F
OR
WS128K32L-XXX O
NLY
)
(TA = -55°C
TO
+125°C), (TA = -40°C
TO
+85°C)
Characteristic
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time (1)
Operation Recovery Time (1)
Sym
V
CC
ICCDR
T
CDR
T
R
Conditions
V
CC
= 2.0V
CS VCC -0.2V
V
IN
V
CC
-0.2V
³
³
Min
2
-
0
T
RC
Typ
-
1
-
Max
-
2
-
-
Units
V
mA
ns
ns
or V
IN
- 0.2V
NOTE:
Parameter guaranteed, but not tested.
3
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White Electronic Designs
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
t
CHZ
1
WS128K32-XXX
AC C
HARACTERISTICS
TO
+125°C)
-25
-35
Min
35
25
35
0
25
15
35
20
3
0
12
12
20
20
3
0
20
20
0
45
25
3
0
20
20
Max
Min
45
45
0
55
30
-45
Max
-55
Min
55
55
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
Max
Symbol
-15
Min
15
15
0
15
10
3
0
12
12
3
0
0
Max
-17
Min
17
17
0
17
10
3
0
12
12
Max Min
20
-20
Max
Min
25
20
0
20
12
3
0
12
12
1
t
OHZ
1
1. This parameter is guaranteed by design but not tested.
(V
CC
= 5.0V, GND = 0V, T
A
= -55°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
AC C
HARACTERISTICS
TO
+125°C)
-35
Min
35
25
25
20
25
0
0
4
15
20
0
0
Max
Min
45
30
30
25
30
0
0
4
25
0
-45
Max
Min
-55
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
25
ns
ns
Max
Symbol
Min
15
14
14
10
14
0
0
3
-15
Max
17
-17
Min
14
15
10
14
0
0
3
Max
Min
20
15
15
12
15
0
0
3
10
0
0
-20
Max
Min
25
20
20
15
20
0
0
3
12
0
-25
WS128K32-XXX /
55
EDI8C32128C
45
45
25
45
0
0
4
t
WHZ
t
DH
1
10
0
1. This parameter is guaranteed by design but not tested.
FIG. 4
AC T
EST
C
IRCUIT
AC T
EST
C
ONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
5
1.5
1.5
Unit
ns
V
V
V
IL
= 0, V
IH
= 3.0 V
Notes:
VZ is programmable from -2V to +7V.
IOL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75
W.
VZ is typically the midpoint of VOH and VOL.
IOL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
4
White Electronic Designs
FIG. 5
T
IMING
W
AVEFORM
-
READ CYCLE
WS128K32-XXX
FIG. 6
W
RITE
C
YCLE
- WE C
ONTROLLED
FIG. 7
W
RITE
C
YCLE
- CS C
ONTROLLED
WS32K32-XHX
5
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
