White Electronic Designs
128Kx32 3.3V SRAM MODULE
FEATURES
Access Times of 15**, 17, 20, 25, 35ns
MIL-STD-883 Compliant Devices Available
Low Voltage Operation
Packaging
• 66-pin, PGA Type, 1.075 inch square Hermetic
Ceramic HIP (Package 400)
• 68 lead, Hermetic CQFP (G2U), 22.4mm (0.880
inch) square (Package 510), 3.56mm (0.140 inch)
high.
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
Commercial, Industrial and Military Temperature
Ranges
WS128K32V-XXX
3.3 Volt Power Supply
Low Power CMOS
TTL Compatible Inputs and Outputs
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
Weight
WS128K32V-XG2UX - 8 grams typical
WS128K32NV-XH1X - 13 grams typical
* This product is subject to change without notice.
** Commercial and Industrial only.
FIGURE 1 – PIN CONFIGURATION FOR WS128K32NV-XH1X
Top View
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
NC
I/O
0
I/O
1
I/O
2
11
22
12
WE
2
#
CS
2
#
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
#
NC
I/O
3
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE#
NC
WE
1
#
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
#
WE
4
#
I/O
27
A
3
A
4
A
5
WE
3
#
CS
3
#
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
66
8
WE
1
# CS
1
#
Pin Description
56
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
Block Diagram
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
OE#
A
0-16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
March 2006
Rev. 8
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WS128K32V-XXX
FIGURE 2 – PIN CONFIGURATION FOR WS128K32V-XG2UX
Top View
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
#
GND
CS
4
#
WE
1
#
A
6
A
7
A
8
A
9
A
10
V
CC
Pin Description
I/O
0-31
A
0-16
WE
1-4
#
CS
1-4
#
OE#
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
3 2 1 68 67 66 65 64 63 62 61
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
WE
1
# CS
1
#
WE
2
# CS
2
#
WE
3
# CS
3
#
WE
4
# CS
4
#
OE#
A
0-16
128K x 8
128K x 8
128K x 8
128K x 8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
1
#
OE#
CS
2
#
NC
WE
2
#
WE
3
#
WE
4
#
NC
NC
NC
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
March 2006
Rev. 8
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
Min
-55
-65
-0.5
-0.5
Max
+125
+150
4.6
150
5.5
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
X
H
WE
X
H
L
H
WS128K32V-XXX
TRUTH TABLE
Mode
Standby
Read
Write
Out Disable
Data I/O
High Z
Data Out
Data In
High Z
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
IH
V
IL
Min
3.0
2.2
-0.3
Max
3.6
V
CC
+ 0.3
+0.8
Unit
V
V
V
CAPACITANCE
T
A
= +25°C, V
IN
= 0V, F = 1.0 MHz
Parameter
OE# capacitance
WE
1-4
# capacitance
HIP (PGA)
CQFP G2U
CS
1-4
# capacitance
Data# I/O capacitance
Address input capacitance
Symbol
C
OE
C
WE
Max
50
20
15
20
20
50
Unit
pF
pF
C
CS
C
I/O
C
AD
pF
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
V
CC
= 3.3V ±0.3V, V
SS
= 0V, -55°C
≤
T
A
≤
+125°C
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
I
CC
x 32
I
SB
V
OL
V
OH
Conditions
V
IN
= GND to V
CC
CS# = V
IH
, OE# = V
IH
, V
OUT
= GND to V
CC
CS# = V
IL
, OE# = V
IH
, f = 5MHz
CS# = V
IH
, OE# = V
IH
, f = 5MHz
I
OL
= 6mA
I
OH
= -4.0mA
Min
Max
10
10
500
32
0.4
Units
μA
μA
mA
mA
V
V
2.4
March 2006
Rev. 8
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
AC CHARACTERISTICS
V
CC
= 3.3V, -55°C
≤
T
A
≤
+125°C
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Symbol
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
1
t
OLZ
1
t
CHZ
1
t
OHZ
1
Min
15
15
0
15
10
5
5
8
8
5
5
9
9
0
17
11
5
5
10
10
-15*
Max
Min
17
17
0
20
12
-17
Max
Min
20
20
-20
Max
WS128K32V-XXX
Min
25
-25
Max
25
Min
35
-35
Max
35
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
25
15
5
5
12
12
0
35
20
5
5
15
15
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
AC Characteristics
V
CC
= 3.3V, -55°C
≤
T
A
≤
+125°C
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
Symbol
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
t
WHZ
1
t
DH
Min
15
13
13
10
13
0
0
5
8
0
0
-15*
Max
Min
17
14
14
11
14
0
0
5
9
0
-17
Max
Min
20
15
15
12
15
0
0
5
10
0
-20
Max
Min
25
20
20
15
20
0
0
5
10
0
-25
Max
Min
35
30
30
18
30
0
0
5
15
-35
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. This parameter is guaranteed by design but not tested.
* Commercial and Industrial only.
FIGURE 3
–
AC TEST CIRCUIT
AC Test Conditions
I
OL
Current Source
D.U.T.
C
eff
= 50 pf
(Bipolar Supply)
V
Z
1.5V
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Output Timing Reference Level
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
I
OH
Current Source
Notes:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z0 = 75 ½.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
March 2006
Rev. 8
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
WS128K32V-XXX
FIGURE 4 – TIMING WAVEFORM - READ CYCLE
CS#
OE#
READ CYCLE 2, (CS# = OE# = V
IL
, WE# = V
IH
)
READ CYCLE 2 (WE# = V
IH
)
FIGURE 5 – WRITE CYCLE - WE# CONTROLLED
CS#
WE#
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 6 – WRITE CYCLE - CS# CONTROLLED
WS32K32-XHX
CS#
WE#
WRITE CYCLE 2, CS# CONTROLLED
March 2006
Rev. 8
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
