WS1M8V-XCX
2x512Kx8 DUALITHIC™ SRAM
PIN CONFIGURATION FOR WS1M8V-XCX
32 DIP
TOP VIEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
ADVANCED*
FEATURES
s
Access Times 17, 20, 25, 35, 45, 55ns
s
Evolutionary, Corner Power/Ground Pinout
s
Packaging:
• 32 pin, Hermetic Ceramic DIP (Package 300)
s
Organized as two banks of 512Kx8
s
Commercial, Industrial and Military Temperature Ranges
s
3.3V Power Supply
s
Low Power CMOS
s
TTL Compatible Inputs and Outputs
s
Output Enable Internally tied to GND.
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A15
A17
WE
A13
A8
A9
A11
CS2
A10
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
3
SRAM DUALITHICS
PIN DESCRIPTION
A
0-18
I/O
0-7
CS
1-2
WE
V
CC
GND
Address Inputs
Data Input/Output
Chip Selects
Write Enable
+3.3V Power Supply
Ground
BLOCK DIAGRAM
I/O
0-7
WE
A
0-18
512K x 8
512K x 8
CS
1
(1)
CS
2
(1)
NOTE:
1. CS
1
and CS
2
are used to select the lower and upper 512Kx8 of the
device. CS
1
and CS
2
must not be enabled at the same time.
October 1998
1
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS1M8V-XCX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
+4.6
150
5.5
Unit
°C
°C
V
°C
V
CS
H
L
L
WE
X
H
L
TRUTH TABLE
Mode
Standby
Read
Write
Data I/O
High Z
Data Out
Data In
Power
Standby
Active
Active
NOTE: OE is internally tied to GND.
RECOMMENDED OPERATING CONDITIONS
CAPACITANCE
(T
A
= +25°C)
Parameter
Input capacitance
Output capicitance
Symbol
C
IN
C
OUT
Condition
V
IN
= 0V, f = 1.0MHz
V
OUT
= 0V, f = 1.0MHz
Max Unit
28
28
pF
pF
V
V
V
3
SRAM DUALITHICS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Symbol
V
CC
V
IH
V
IL
T
A
Min
3.0
2.2
-0.3
-55
Max
3.6
V
CC
+ 0.3
+0.8
+125
Unit
This parameter is guaranteed by design but not tested.
°C
DC CHARACTERISTICS
(V
CC
= 3.3V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current
Standby Current
Output Low Voltage
Output High Voltage
Sym
I
LI
I
LO
1
1
1
Conditions
Min
V
CC
= 3.6, V
IN
= GND to V
CC
CS = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, f = 5MHz, Vcc = 3.6
CS = V
IH
, f = 5MHz, Vcc = 3.6
I
OL
= 8.0mA
I
OH
= -4.0mA
2.4
Max
10
10
160
30
0.4
Units
µA
µA
mA
mA
V
V
I
CC
I
SB
V
OL
V
OH
NOTE: DC test conditions: V
IH
= V
CC
-0.3V , V
IL
= 0.3V
1. OE is internally tied to GND.
White Microelectronics • Phoenix, AZ • (602) 437-1520
2
WS1M8V-XCX
AC CHARACTERISTICS
(V
CC
= 3.3V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Chip Select to Output in Low Z
Chip Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
CLZ
1
Symbol
Min
17
-17
Max
-20
Min
20
17
20
0
17
20
2
9
10
2
0
Max
Min
25
-25
Max
Min
35
25
0
25
4
12
-35
Max
-45
Min
45
35
0
35
4
15
20
45
4
45
0
Max
-55
Min
55
55
Max
Units
ns
ns
ns
55
ns
ns
20
ns
0
2
t
CHZ
1
1. This parameter is guaranteed by design but not tested.
2. OE is internally tied to GND.
3
SRAM DUALITHICS
AC CHARACTERISTICS
(V
CC
= 3.3V, GND = 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
Symbol
-17
Min
17
14
14
9
14
0
0
2
9
0
0
Max
-20
Min
20
14
14
10
14
0
0
3
9
0
Max
-25
Min
25
15
15
10
15
0
0
4
10
0
Max
Min
35
25
25
20
25
0
0
4
-35
Max
-45
Min
45
35
35
25
35
0
5
5
15
0
15
0
Max
-55
Min
55
50
50
25
40
0
5
5
25
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WHZ
1
t
DH
1. This parameter is guaranteed by design but not tested.
AC TEST CIRCUIT
I
OL
Current Source
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
Typ
V
IL
= 0, V
IH
= 2.5
5
1.5
1.5
Unit
V
ns
V
V
D.U.T.
C
eff
= 50 pf
V
Z
≈
1.5V
Output Timing Reference Level
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
3
White Microelectronics • Phoenix, AZ • (602) 437-1520
WS1M8V-XCX
TIMING WAVEFORM - READ CYCLE
t
RC
ADDRESS
t
RC
ADDRESS
t
AA
CS
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
ACS
t
CLZ
DATA I/O
HIGH IMPEDANCE
DATA VALID
t
CHZ
3
SRAM DUALITHICS
READ CYCLE 1 (CS = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
NOTE: OE is internally tied to GND.
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
WRITE CYCLE - CS CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
AS
t
AW
t
CW
t
AH
CS
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
White Microelectronics • Phoenix, AZ • (602) 437-1520
4
WS1M8V-XCX
PACKAGE 300:
32 PIN, CERAMIC DIP, SINGLE CAVITY SIDE BRAZED
42.4 (1.670)
±
0.4 (0.016)
15.04 (0.592)
±
0.3 (0.012)
4.34 (0.171)
±
0.79 (0.031)
PIN 1 IDENTIFIER
3.2 (0.125) MIN
0.84 (0.033)
±
0.4 (0.014)
2.5 (0.100)
TYP
1.27 (0.050)
±
0.1 (0.005)
0.46 (0.018)
±
0.05 (0.002)
0.25 (0.010)
±
0.05 (0.002)
15.25 (0.600)
±
0.25 (0.010)
3
SRAM DUALITHICS
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
ORDERING INFORMATION
W S 1M8 V - XXX C X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE:
C = Ceramic 0.600" DIP (Package 300)
ACCESS TIME (ns)
Low Voltage Supply 3.3V
±
10%
ORGANIZATION, two banks of 512K x 8
SRAM
WHITE MICROELECTRONICS
5
White Microelectronics • Phoenix, AZ • (602) 437-1520
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