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WS512K32-55NH1CA

SRAM Module, 512KX32, 55ns, CMOS, CPGA66, 1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66

器件类别:存储    存储   

厂商名称:Microsemi

厂商官网:https://www.microsemi.com

下载文档
器件参数
参数名称
属性值
是否Rohs认证
不符合
包装说明
1.075 X 1.075 INCH, HERMETIC SEALED, CERAMIC, HIP-66
Reach Compliance Code
unknown
最长访问时间
55 ns
其他特性
USER CONFIGURABLE AS 2M X 8
备用内存宽度
16
JESD-30 代码
S-CPGA-P66
长度
27.3 mm
内存密度
16777216 bit
内存集成电路类型
SRAM MODULE
内存宽度
32
功能数量
1
端子数量
66
字数
524288 words
字数代码
512000
工作模式
ASYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
512KX32
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装代码
PGA
封装形状
SQUARE
封装形式
GRID ARRAY
并行/串行
PARALLEL
峰值回流温度(摄氏度)
NOT SPECIFIED
认证状态
Not Qualified
座面最大高度
4.34 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
COMMERCIAL
端子形式
PIN/PEG
端子节距
2.54 mm
端子位置
PERPENDICULAR
处于峰值回流温度下的最长时间
NOT SPECIFIED
宽度
27.3 mm
文档预览
WS512K32-XXX
HI-RELIABILITY PRODUCT
512Kx32 SRAM MODULE, SMD 5962-94611
FEATURES
s
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
s
Packaging
• 66 pin, PGA Type, 1.075" square, Hermetic Ceramic HIP
(Package 400).
• 68 lead, 40mm Hermetic Low Profile CQFP, 3.5mm (0.140")
(Package 502), Package to be developed.
• 68 lead, Hermetic CQFP (G2T), 22.4mm (0.880") square
(Package 509) 4.57mm (0.180") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
• 68 lead, Hermetic CQFP (G1U), 22.4mm (0.880") square
(Package 519) 3.57mm (0.140") height.
Designed to fit JEDEC 68 lead 0.990" CQFJ footprint (Fig. 3).
s
Organized as 512Kx32, User Configurable as 1Mx16 or 2Mx8
s
Commercial, Industrial and Military Temperature Ranges
s
TTL Compatible Inputs and Outputs
s
5 Volt Power Supply
s
Low Power CMOS
s
Built-in Decoupling Caps and Multiple Ground Pins for Low
Noise Operation
s
Weight
WS512K32-XH1X - 13 grams typical
WS512K32-XG2TX - 13 grams typical
WS512K32-XG1UX - 13 grams typical
WS512K32-XG4TX - 20 grams typical
* 15ns Access Time available only in Commercial and Industrial Temperature.
This speed is not fully characterized and is subject to change without notice.
FIG. 1
1
I/O
8
I/O
9
I/O
10
A
13
A
14
A
15
A
16
A
17
I/O
0
I/O
1
I/O
2
11
PIN CONFIGURATION FOR WS512K32N-XH1X
TOP VIEW
12
WE
2
CS
2
GND
I/O
11
A
10
A
11
A
12
V
CC
CS
1
NC
I/O
3
22
33
23
I/O
15
I/O
14
I/O
13
I/O
12
OE
A
18
WE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
24
I/O
25
I/O
26
A
6
A
7
NC
A
8
A
9
I/O
16
I/O
17
I/O
18
44
34
V
CC
CS
4
WE
4
I/O
27
A
3
A
4
A
5
WE
3
CS
3
GND
I/O
19
55
45
I/O
31
I/O
30
I/O
29
I/O
28
A
0
A
1
A
2
I/O
23
I/O
22
I/O
21
I/O
20
8
8
8
8
PIN DESCRIPTION
56
I/O
0-31
A
0-18
WE
1-4
CS
1-4
OE
V
CC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
BLOCK DIAGRAM
W E
1
CS
1
OE
A
0
-
18
512K x 8
512K x 8
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
512K x 8
512K x 8
66
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
November 1999 Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
FIG. 2
PIN CONFIGURATION FOR WS512K32-XG4TX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
1
GND
CS
3
WE
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-18
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
8
8
8
WE
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
CS
1-4
OE
V
CC
GND
NC
BLOCK DIAGRAM
CS
1
WE
OE
A
0-18
512K x 8
512K x 8
CS
2
CS
3
CS
4
512K x 8
512K x 8
8
V
CC
A
11
A
12
A
13
A
14
A
15
A
16
CS
2
OE
CS
4
A
17
A
18
NC
NC
NC
NC
NC
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
FIG. 3
PIN CONFIGURATION FOR WS512K32-XG2TX
AND WS512K32-XG1UX
TOP VIEW
NC
A
0
A
1
A
2
A
3
A
4
A
5
CS
3
GND
CS
4
WE
1
A
6
A
7
A
8
A
9
A
10
V
CC
PIN DESCRIPTION
I/O
0-31
A
0-18
I/O
16
I/O
17
I/O
18
I/O
19
I/O
20
I/O
21
I/O
22
I/O
23
GND
I/O
24
I/O
25
I/O
26
I/O
27
I/O
28
I/O
29
I/O
30
I/O
31
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
Not Connected
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
GND
I/O
8
I/O
9
I/O
10
I/O
11
I/O
12
I/O
13
I/O
14
I/O
15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CS
2
A
17
WE
2
WE
3
WE
4
A
11
A
12
A
13
A
14
A
15
A
16
V
CC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CS
1
A
18
OE
WE
1-4
CS
1-4
OE
0.940"
V
CC
GND
NC
The White 68 lead G2T/G1U
CQFP fills the same fit and
function as the JEDEC 68 lead
CQFJ or 68 PLCC. But the G2T/
G1U has the TCE and lead
inspection advantage of the
CQFP form.
OE
A
0
-
18
BLOCK DIAGRAM
W E
2
CS
2
W E
3
CS
3
W E
4
CS
4
W E
1
CS
1
NC
NC
512K x 8
512K x 8
512K x 8
512K x 8
8
8
8
8
I/O
0-7
I/O
8-15
I/O
16-23
I/O
24-31
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
2
WS512K32-XXX
ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Junction Temperature
Supply Voltage
Symbol
T
A
T
STG
V
G
T
J
V
CC
-0.5
Min
-55
-65
-0.5
Max
+125
+150
Vcc+0.5
150
7.0
Unit
°C
°C
V
°C
V
CS
H
L
L
L
OE
X
L
H
X
WE
X
H
H
L
TRUTH TABLE
Mode
Standby
Read
Out Disable
Write
Data I/O
High Z
Data Out
High Z
Data In
Power
Standby
Active
Active
Active
RECOMMENDED OPERATING CONDITIONS
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temp (Mil)
Symbol
V
CC
V
IH
V
IL
T
A
Min
4.5
2.2
-0.5
-55
Max
5.5
V
CC
+ 0.3
+0.8
+125
Unit
V
V
V
°C
Parameter
OE capacitance
WE
1-4
capacitance
HIP (PGA)
CQFP G4T
CQFP G2T/G1U
CS
1-4
capacitance
Data I/O capacitance
Address input capacitance
CAPACITANCE
(T
A
= +25°C)
Symbol
C
OE
C
WE
Conditions
V
IN
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
50
20
C
CS
C
I/O
C
AD
V
IN
= 0 V, f = 1.0 MHz
V
I/O
= 0 V, f = 1.0 MHz
V
IN
= 0 V, f = 1.0 MHz
20
20
50
pF
pF
pF
Max
50
Unit
pF
pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Supply Current x 32 Mode
Standby Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC x 32
I
SB
V
OL
V
OH
Conditions
Min
V
CC
= 5.5, V
IN
= G
ND
to V
CC
CS = V
IH
, OE = V
IH
, V
OUT
= GND to V
CC
CS = V
IL
, OE = V
IH
, f = 5MHz, Vcc = 5.5
CS = V
IH
, OE = V
IH
, f = 5MHz, Vcc = 5.5
I
OL
= 8mA for 15 - 35ns,
I
OL
= 2.1mA for 45 - 55ns, Vcc = 4.5
I
OH
= -4.0mA for 15 - 35ns,
I
OH
= -1.0mA for 45 - 55ns, Vcc = 4.5
2.4
Max
10
10
540
80
0.4
Units
µA
µA
mA
mA
V
V
NOTE:
DC test conditions: V
IH
= V
CC
-0.3V, V
IL
= 0.3V
DATA RETENTION CHARACTERISTICS
(T
A
= -55°C to +125°C)
Parameter
Data Retention Supply Voltage
Data Retention Current
Symbol
V
DR
I
CCDR1
Conditions
Min
CS
V
CC
-0.2V
V
CC
= 3V
2.0
3.2
Typ
Max
5.5
28*
V
mA
Units
* Also available in Low Power version, please call factory for information.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
WS512K32-XXX
AC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Read Cycle
Read Cycle Time
Address Access Time
Output Hold from Address Change
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
t
RC
t
AA
t
OH
t
ACS
t
OE
t
CLZ
t
OLZ
1
Symbol
-15*
Min
15
15
0
15
8
2
0
12
12
2
0
0
Max
Min
17
-17
Max
Min
20
17
0
17
9
2
0
12
12
-20
Max
Min
25
20
0
20
10
2
0
12
12
-25
Max
Min
35
25
0
25
12
4
0
12
12
-35
Max
Min
45
35
0
35
25
4
0
15
15
-45
Max
-55
Min
55
45
0
45
25
4
0
20
20
20
20
55
25
55
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
t
CHZ
1
t
OHZ
1
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C to +125°C)
Parameter
Write Cycle
Write Cycle Time
Chip Select to End of Write
Address Valid to End of Write
Data Valid to End of Write
Write Pulse Width
Address Setup Time
Address Hold Time
Output Active from End of Write
Write Enable to Output in High Z
Data Hold Time
t
WC
t
CW
t
AW
t
DW
t
WP
t
AS
t
AH
t
OW
1
Symbol
-15*
Min
15
13
13
10
13
2
0
2
8
0
0
Max
17
15
15
11
15
2
0
2
-17
Min
Max
20
15
15
12
15
2
0
3
9
0
-20
Min
Max
Min
25
17
17
13
17
2
0
4
11
0
-25
Max
Min
35
25
25
20
25
2
0
4
13
0
-35
Max
45
35
35
25
35
2
5
5
15
0
-45
Min
Max
55
50
50
25
40
2
5
5
20
0
-55
Min Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
ns
t
WHZ
1
t
DH
* 15ns Access Time available only in Commercial and Industrial Temperature. This speed is not fully characterized and is subject to change without notice.
1. This parameter is guaranteed by design but not tested.
2. The Address Setup Time of minimum 2ns is for the G2T, G1U and H1 packages. t
AS
minimum for the G4T package is 0ns.
FIG. 4
AC TEST CIRCUIT
Current Source
I
OL
AC TEST CONDITIONS
Parameter
Input Pulse Levels
Input Rise and Fall
Input and Output Reference Level
D.U.T.
V
Z
Typ
V
IL
= 0, V
IH
= 3.0
5
1.5
1.5
Unit
V
ns
V
V
1.5V
Output Timing Reference Level
C
eff
= 50 pf
(Bipolar Supply)
I
OH
Current Source
NOTES:
V
Z
is programmable from -2V to +7V.
I
OL
& I
OH
programmable from 0 to 16mA.
Tester Impedance Z
0
= 75
Ω.
V
Z
is typically the midpoint of V
OH
and V
OL
.
I
OL
& I
OH
are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
4
WS512K32-XXX
FIG. 5
TIMING WAVEFORM - READ CYCLE
ADDRESS
t
RC
t
AA
CS
t
RC
ADDRESS
t
ACS
t
CLZ
OE
t
CHZ
t
AA
t
OH
DATA I/O
PREVIOUS DATA VALID
DATA VALID
t
OE
t
OLZ
DATA I/O
HIGH IMPEDANCE
t
OHZ
DATA VALID
READ CYCLE 1 (CS = OE = V
IL
, WE = V
IH
)
READ CYCLE 2 (WE = V
IH
)
FIG. 6
WRITE CYCLE - WE CONTROLLED
t
WC
ADDRESS
t
AW
t
CW
CS
t
AH
t
AS
WE
t
WP
t
OW
t
WHZ
t
DW
t
DH
DATA I/O
DATA VALID
WRITE CYCLE 1, WE CONTROLLED
FIG. 7
WRITE CYCLE - CS CONTROLLED
t
WC
ADDRESS
WS32K32-XHX
t
CW
t
AH
t
AS
CS
t
AW
t
WP
WE
t
DW
DATA I/O
DATA VALID
t
DH
WRITE CYCLE 2, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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