Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3V ± 0.3V Power Supply
168 Pin DIMM
• PCB: 29.41mm (1.158")
WV3DG64127V-D2
ADVANCED*
DESCRIPTION
The WV3DG64127V is a 2x64Mx64 synchronous DRAM
module which consists of sixteen stacked 64Mx8 bit
with 4 banks SDRAM components in TSOP II package
and one 2K EEPROM which are mounted on a 168 Pin
DIMM multilayer FR4 Substrate.
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CBO
CB1
Vss
NC
NC
V
CC
WE#
DQM0
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0#
DNU
V
SS
A0
A2
A4
A6
A8
A10/AP
BA1
V
CC
V
CC
CLK0
V
SS
DNU
CS2#
DQM2
DQM3
DNU
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
V
CC
DQ20
NC
NC
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
NC
SDA
SCL
V
CC
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
CC
CAS#
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1#
RAS#
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
CC
CLK1
A12
V
SS
CKE0
CS3#
DQM6
DQM7
NC
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
CC
DQ52
NC
NC
DNU
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
SA0
SA1
SA2
V
CC
PIN NAMES
A0 – A12
BA0-1
DQ0-63
CLK0-CLK3
CKE0, CKE1
CS0# - CS3#
RAS#
CAS#
WE#
DQM0-7
V
CC
V
SS
SDA
SCL
DNU
NC
Address input (Multiplexed)
Select Bank
Data Input/Output
Clock input
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply
Ground
Serial data I/O
Serial clock
Do not use
No Connect
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQM0
WV3DG64127V-D2
ADVANCED*
DQM4
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQM1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQM5
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS3#
CS2#
DQM2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM6
DQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQM3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQM7
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
A0 ~ A12, BA0 & 1
RAS#
CAS#
WE#
CKE0
SDRAM
SDRAM
SCL
SDA
A0
A1
A2
V
CC
SDRAM
SDRAM
SDRAM
10K Ω
SA0 SA1 SA2
CKE1
10Ω
DQn
V
CC
Two 0.1uF Capacitors
per each SDRAM
Vss
To all SDRAMs
SDRAM
SDRAM
10Ω
CK0/1/2/3
Every DQpin of SDRAM
SDRAM
SDRAM
SDRAM
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
TSTG
PD
IOS
WV3DG64127V-D2
ADVANCED*
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
32
50
Units
V
V
°C
W
mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0°C
≤
T
A
≤
+70°C
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
V
CC
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
—
-10
Typ
3.3
3.0
—
—
—
—
Max
3.6
V
CCQ
+0.3
0.8
—
0.4
10
Unit
V
V
V
V
V
µA
1
2
I
OH
= -2mA
I
OL
= -2mA
3
Note
Note:
1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ V
IN
≤ V
CC
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V, V
REF
=1.4V
±
200mV
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0-CKE1)
Input Capacitance (CK0-CK3)
Input Capacitance (CS0#-CS3#)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
Max
150
150
80
45
45
30
150
30
Unit
pF
pF
pF
pF
pF
pF
pF
pF
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
I
DD
SPECIFICATIONS AND CONDITIONS
V
CC
, V
CCQ
= +3.3V ±0.3V; SDRAM component values only
WV3DG64127V-D2
ADVANCED*
Version
Parameter
Operating current
(One bank active)
Precharge standby current
in power-down mode
Symbol
I
CC1
I
CC2P
I
CC2PS
I
CC2N
I
CC2NS
I
CC3P
I
CC3PS
I
CC3N
I
CC3NS
Test Condition
7
Burst length = 1, t
RC
≥ t
RC
(min), IO = 0 mA
CKE ≤ V
IL
(max), t
CC
= 10ns
CKE & CLK ≥ V
IL
(max), t
CC
= ∞
CKE ≥ V
IH
(min), CS# ≥ VIH(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE ≥ V
IH
(min), CLK ≤ V
IL
(max), t
CC
= ∞
Input signals are stable
CKE ≤ V
IL
(max), t
CC
= 10ns
CKE & CLK ≤ V
IL
(max), t
CC
= ∞
CKE ≥ V
IH
(min), CS# ≥ V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE ≥ V
IH
(min), CLK ≤ V
IL
(max), t
CC
= ∞
Input signals are stable
IO = 0 mA
Page burst
4banks Activated.
t
CCD
= 2CLKs
t
RC
≥ t
RC
(min)
CKE ≤ 0.2V
C
2080
75
1920
64
64
640
320
200
200
960
800
mA
mA
mA
mA
10
1920
mA
mA
1
Unit
Note
Precharge standby current
in non power-down mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
Operating current
(Burst mode)
Refresh current
Self refresh current
I
CC4
2240
2240
2080
mA
1
I
CC5
I
CC6
4000
3680
96
3520
mA
mA
2
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing is CMOS (V
IH
/V
IL
= V
CCQ
/V
JSQ
)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
AC OPERATING TEST CONDITIONS
V
CC
, V
CCQ
= +3.3v ±0.3V, 0°C - 70°C
Parameter
AC input levels (V
IH
/V
IL
)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4/0.4
1.4
t
R
/t
F
= 1/1
1.4
See Fig. 2
WV3DG64127V-D2
ADVANCED*
Unit
V
V
ns
V
DC OUTPUT LOAD CIRCUIT
3.3V
AC OUTPUT LOAD CIRCUIT
Vtt = 1.4V
1200Ω
Output
870Ω
50pF
V
OH
(DC) = 2.4V, I
OH
= -2mA
V
OL
(DC) = 0.4V, I
OL
= 2mA
50Ω
Output
Z0 = 50Ω
50pF
OPERATING AC PARAMETER
V
CC
, V
CCQ
= +3.3v ±0.3V, 0°C - 70°C)
Parameter
Row active to row active delay
RAS# to CAS# delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Symbol
t
RRD(min)
t
RCD(min)
t
RP(min)
t
RAS(min)
t
RAS(max)
t
RC(min)
t
RDL(min)
t
DAL(min)
t
CDL(min)
t
BDL(min)
t
CCD(min)
CAS latency=3
CAS latency=2
7
15
15
15
45
60
Version
75
15
20
20
45
100
65
2
2 CLK + tRP
1
1
1
2
1
Unit
10
20
20
20
50
70
ns
ns
ns
ns
us
ns
CLK
—
CLK
CLK
CLK
ea
Note
1
1
1
1
1
2
2
2
3
4
Notes:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
频谱分析仪的电流模式一般有自10Hz低频起始的频率响应。当与1Hz或带宽更窄的 FET 软件结合使用时，现代频谱分析仪就具备了扩展的低频性能，使之成为设计与调试高性能模拟电路不可或缺的工具。不幸的是，主要面向RF应用的频谱分析仪典型输入阻抗为50Ω，当用于许多高阻抗模拟电路时，这是一个重负载。与 50Ω输入串接一个 953Ω电阻器可以改善阻抗显得略高的探头，但这种方法也只能提供1kΩ的输入阻抗，而...[详细]
FPGA/CPLD
