White Electronic Designs
WV3EG265M64EFSU-D4
1GB – 2x64Mx64 DDR SDRAM UNBUFFERED, w/PLL
FEATURES
Double-data-rate architecture
PC2700 and PC2100
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2, 2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Auto and self refresh, (8K/64ms refresh)
Serial presence detect with EEPROM
Power supply: V
CC
/V
CCQ
: 2.5V ± 0.2V
Dual Rank
200 pin SO-DIMM package
•
Package height options:
D4: 31.75 mm (1.25”)
* This product is subject to change without notice.
DESCRIPTION
The WV3EG265M64EFSU is a 2x64Mx64 Double Data
Rate SDRAM memory module based on 512Mb DDR
SDRAM component. The module consists of sixteen
64Mx8 bit with 4 banks DDR SDRAMs in FBGA packages
mounted on a 200 pin substrate.
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333 @CL=2.5
Clock Speed
CL-t
RCD
-t
RP
166MHz
2.5-3-3
DDR266 @CL=2
133MHz
2-2-2
DDR266 @CL=2.5
133MHz
2.5-3-3
October 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
SYMBOL PIN#
V
REF
51
V
REF
52
53
V
SS
V
SS
54
DQ0
55
DQ4
56
DQ1
57
DQ5
58
59
V
CC
V
CC
60
DQS0
61
DM0
62
DQ2
63
DQ6
64
65
V
SS
V
SS
66
DQ3
67
DQ7
68
DQ8
69
DQ12
70
V
CC
71
72
V
CC
DQ9
73
DQ13
74
DQS1
75
DM1
76
V
SS
77
78
V
SS
DQ10
79
DQ14
80
DQ11
81
DQ15
82
V
CC
83
V
CC
84
CK0
85
V
CC
86
CK0#
87
V
SS
88
V
SS
89
V
SS
90
DQ16
91
DQ20
92
DQ17
93
DQ21
94
95
V
CC
V
CC
96
DQS2
97
DM2
98
DQ18
99
DQ22
100
SYMBOL PIN#
V
SS
101
V
SS
102
DQ19
103
DQ23
104
DQ24
105
DQ28
106
V
CC
107
V
CC
108
DQ25
109
DQ29
110
DQS3
111
DM3
112
V
SS
113
V
SS
114
DQ26
115
DQ30
116
DQ27
117
DQ31
118
V
CC
119
V
CC
120
NC
121
NC
122
NC
123
NC
124
V
SS
125
V
SS
126
NC
127
NC
128
NC
129
NC
130
V
CC
131
V
CC
132
NC
133
NC
134
NC
135
NC
136
V
SS
137
V
SS
138
NC
139
V
SS
140
NC
141
V
CC
142
V
CC
143
V
CC
144
CKE1
145
CKE0
146
NC
147
NC
148
A12
149
A11
150
SYMBOL PIN#
A9
151
A8
152
V
SS
153
V
SS
154
A7
155
A6
156
A5
157
A4
158
A3
159
A2
160
A1
161
A0
162
V
CC
163
V
CC
164
A10
165
BA1
166
BA0
167
RAS#
168
WE#
169
CAS#
170
CS0#
171
CS1#
172
NC
173
NC
174
V
SS
175
V
SS
176
DQ32
177
DQ36
178
DQ33
179
DQ37
180
V
CC
181
V
CC
182
DQS4
183
DM4
184
DQ34
185
DQ38
186
V
SS
187
V
SS
188
DQ35
189
DQ39
190
DQ40
191
DQ44
192
V
CC
193
V
CC
194
DQ41
195
DQ45
196
DQS5
197
DM5
198
V
SS
199
V
SS
200
SYMBOL
DQ42
DQ46
DQ43
DQ47
V
CC
V
CC
V
CC
NC
V
SS
NC
V
SS
V
SS
DQ48
DQ52
DQ49
DQ53
V
CC
V
CC
DQS6
DM6
DQ50
DQ54
V
SS
V
SS
DQ51
DQ55
DQ56
DQ60
V
CC
V
CC
DQ57
DQ61
DQS7
DM7
V
SS
V
SS
DQ58
DQ62
DQ59
DQ63
V
CC
V
CC
SDA
SA0
SCL
SA1
V
CCSPD
SA2
NC
NC
WV3EG265M64EFSU-D4
PIN DESCRIPTION
A0-A12
BA0-BA1
DQ0-DQ63
DQS0-DQS7
CK0, CK0#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
DM0-DM7
V
CC
V
CCQ
V
SS
V
REF
V
CCSPD
SDA
SCL
SA0-SA2
NC
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-In Mask
Power Supply (2.5V)
Power Supply for DQS (2.5V)
Ground
Power Supply for Reference
Serial EEPROM Power Supply
(2.3V to 3.6V)
Serial data I/O
Serial clock
Address in EEPROM
No Connect
October 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3EG265M64EFSU-D4
FUNCTIONAL BLOCK DIAGRAM
CS1#
CS0#
DQS0
DM0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS4
DM4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS1
DM1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS5
DM5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS2
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS6
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS3
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
DQS7
DM7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S0#
DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S1#
BA0-BA1
A0-A12
RAS#
CAS#
WE#
CS1#
CS0#
BA0-BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
WE#: DDR SDRAMs
CS1#: DDR SDRAMs
CS0#: DDR SDRAMs
SERIAL PD
CK0
CK0#
PLL
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
V
CCSPD
V
CC
/V
CCQ
V
REF
V
SS
SPD
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
SCL
WP
A0
SA0
A1
SA1
A2
SA2
SDA
NOTE: All datalines are terminated through a 22 ohm series resistor
October 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Voltage on V
CCQ
supply relative to V
SS
Storage Temperature
Operating Temperature
Power Dissipation
Short Circuit Current
WV3EG265M64EFSU-D4
ABSOLUTE MAXIMUM RATINGS
Symbol
V
IN
, V
OUT
V
CC
V
CCQ
T
STG
T
A
P
D
I
OS
Value
-0.5 to 3.3
-1.0 to 3.6
-1.0 to 3.6
-55 to +150
0 to +70
16
50
Units
V
V
V
°C
°C
W
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC CHARACTERISTICS
0°C
≤
T
A
≤
70°C, V
CC
= 2.5V ± 0.2V
Symbol
V
CC
V
CCQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
V
IX
(DC)
Addr, CAS#,
RAS#, WE#
CS#, CKE
CK, CK#
DM
Parameter
Supply voltage DDR266/DDR333 (nominal V
CC
of 2.5V)
I/O Supply voltage DDR266/DDR333 (nominal V
CC
of 2.5V)
I/O Reference voltage
I/O Termination voltage
Input logic high voltage
Input logic low voltage
Input voltage level, CK and CK#
Input differential voltage, CK and CK#
Input crossing point voltage, CK and CK#
Min
2.3
2.3
0.49*V
CCQ
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.3
0.3
-32
-16
-10
-4
-10
-16.8
16.8
-9
9
Max
2.7
2.7
0.51*V
CCQ
V
REF
+0.04
V
CCQ
+0.30
V
REF
-0.15
V
CCQ
+0.30
V
CCQ
+0.60
V
CCQ
+0.60
32
16
-10
4
10
—
—
—
—
Unit
V
V
V
V
V
V
V
V
uA
uA
uA
uA
uA
mA
mA
mA
mA
Note
1
2
3
Input leakage current
I
I
Output leakage current
Output high current (normal strengh); V
OUT
= V +0.84V
Output high current (normal strengh); V
OUT
= V
TT
-0.84V
Output high current (half strengh); V
OUT
= V
TT
+0.45V
Output high current (half strengh); V
OUT
= V
TT
-0.45V
I
OZ
I
OH
I
OL
I
OH
I
OL
NOTES:
1. V
REF
is expected to be equal to 0.5*V
CCQ
of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on V
REF
may not exceed ±2% of the DC
value
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to V
REF
, and must track variations in the DC level of V
REF
3. V
ID
is the magnitude of the difference between the input level on CK and the input level on CK#.
CAPACITANCE
V
CC
= 2.5V, V
CCQ
= 2.5V, T
A
= 25°C, f = 1MHz
Parameter
Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#)
Input Capacitance (CKE0, CKE1)
Input Capacitance (CS0#, CS1#)
Input Capacitance (CLK0, CLK0#)
Input Capacitance (DM0-DM7)
Data and DQS input/output capacitance (DQ0-DQ63)
October 2005
Rev. 1
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
OUT1
Min
28
16
16
6
11
11
Max
44
24
24
7.5
13
13
Unit
pF
pF
pF
pF
pF
pF
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WV3EG265M64EFSU-D4
I
DD
SPECIFICATIONS AND TEST CONDITIONS
Recommended operating conditions, 0°c
≤
T
A
≤
70°C, V
CCQ
= 2.5V ± 0.2V, V
CC
= 2.5V ± 0.2V
Parameter
Symbol
Conditions
One device bank active; Active-Precharge; t
RC
= t
RC(MIN)
;
t
CK
= t
CK(MIN)
; DQ, DM and DQS inputs change once per clock
cycle; Address and control inputs change once every two
clock cycles
One device bank; Active-Read-Precharge; BL = 4;
t
RC
= t
RC(MIN)
; t
CK
= t
CK(MIN)
; I
OUT
= 0mA; Address and control
inputs change once per clock cycle
All device banks are idle; Power-down mode; t
CK
= t
CK(MIN)
;
CKE = LOW
CS# = HIGH; All device banks are idle; t
CK
= t
CK(MIN)
;
CKE = HIGH; Address and other control inputs changing once
per clock cycle. V
IN
= V
REF
for DQ, DQS and DM
One device bank active; Power-down mode; t
CK
= t
CK(MIN)
;
CKE = LOW
CS# = HIGH; CKE = HIGH; One device bank active;
t
RC
= t
RAS(MAX)
; t
CK
= t
CK(MIN)
; DQ, DM and DQS inputs change
twice per clock cycle; Address and other control inputs
changing once per clock cycle
Burst = 2; Reads; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; t
CK
= t
CK(MIN)
; I
OUT
= 0mA
Burst = 2; Writes; Continuous burst; One device bank active;
Address and other control inputs changing once per clock
cycle; t
CK
= t
CK(MIN)
; DQ, DM and DQS inputs change twice per
clock cycle
t
RC
= t
RFC(MIN)
CKE < 0.2V
Four device bank interleaving Reads Burst = 4 with auto
precharge; t
RC
= t
RFC(MIN)
; t
CK
= t
CK(MIN)
; Address and control
inputs change only during Active READ, or WRITE commands
DDR333 @
CL = 2.5
DDR266 @
CL = 2
DDR266 @
CL = 2.5
Unit
Operating current
I
DD0*
1360
1240
1240
mA
Operating current
Percharge power-
down standby current
Idle standby current
Active power-down
standby current
Active standby
current
I
DD1*
1600
1480
1480
mA
I
DD2P**
360
360
360
mA
I
DD2F**
1000
920
920
mA
I
DD3P**
840
760
760
mA
I
DD3N**
1080
1000
1000
mA
Operating current
I
DD4R*
1640
1480
1480
mA
Operating current
I
DD4W*
1720
1400
1400
mA
Auto refresh current
Self refresh current
Orerating current
I
DD5**
I
DD6**
I
DD7*
4920
360
3560
4760
360
3120
4760
360
3120
mA
mA
mA
NOTE:
I
DD
specification is based on Micron components. Other DRAM Manufacturers specification may be different.
* Value calculated as one module rank in this operating condition and all other module ranks in I
DD2P
(CKE low) mode.
** Value calculated reflects all module ranks in this operating condition.
AC OPERATING TEST CONDITIONS
Parameter/Condition
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Differential Voltage, CK and CK# inputs
Input Crossing Point Voltage, CK and CK3 inputs
Symbol
V
IH(AC)
V
IL(AC)
V
ID(AC)
V
IX(AC)
0.7
0.5*V
CCQ
-0.2
Min
V
REF
+0.31
V
REF
-0.31
V
CCQ
+0.6
0.5*V
CCQ
+0.2
Max
Unit
V
V
V
V
October 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
