X1228
DED F O R
OMMEN
NOT REC DESIGNS
NEW
12028
SEE IS L
DATASHEET
FN8100
Rev 4.00
May 18, 2006
4K (512 x 8), 2-Wire ™ RTC Real Time Clock/Calendar/CPU Supervisor with
EEPROM
FEATURES
• Real Time Clock/Calendar
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to
±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I
2
C*
— 400kHz Data Transfer Rate
• Frequency Output (SW Selectable: Off, 1Hz,
•
•
•
•
•
4096Hz, or 32.768kHz)
Low Power CMOS
— 1.25µA Operating Current (Typical)
Small Package Options
— 14 Ld SOIC and 14 Ld TSSOP
Repetitive Alarms
Temperature Compensation
Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Utility Meters
HVAC Equipment
Audio/Video Components
Set Top Box/Television
Modems
Network Routers, Hubs, Switches, Bridges
Cellular Infrastructure Equipment
Fixed Broadband Wireless Equipment
Pagers/PDA
POS Equipment
Test Meters/Fixtures
Office Automation (Copiers, Fax)
Home Appliances
Computer Products
Other Industrial/Medical/Automotive
BLOCK DIAGRAM
OSC Compensation
32.768kHz
X1
X2
Oscillator
Frequency
Divider
1Hz
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
Battery
Switch
Circuitry
V
CC
V
BACK
PHZ/IRQ
Select
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Mask
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
Alarm
Compare
Alarm Regs
(EEPROM)
4K
EEPROM
ARRAY
8
RESET
Watchdog
Timer
Low Voltage
Reset
FN8100 Rev 4.00
May 18, 2006
Page 1 of 29
X1228
Ordering Information
PART NUMBER
X1228S14-4.5A
X1228S14Z-4.5A (Note)
X1228S14I-4.5A
X1228S14IZ-4.5A (Note)
X1228V14-4.5A
X1228V14Z-4.5A (Note)
X1228V14I-4.5A
X1228V14IZ-4.5A (Note)
X1228S14
X1228S14Z (Note)
X1228S14I
X1228S14IZ (Note)
X1228V14
X1228V14Z (Note)
X1228V14I
X1228V14IZ (Note)
X1228S14-2.7A
X1228S14Z-2.7A (Note)
X1228S14I-2.7A
X1228S14IZ-2.7A (Note)
X1228V14-2.7A
X1228V14Z-2.7A (Note)
X1228V14I-2.7A
X1228V14IZ-2.7A (Note)
X1228S14-2.7*
X1228S14Z-2.7* (Note)
X1228S14I-2.7
X1228S14IZ-2.7 (Note)
X1228V14-2.7
X1228V14Z-2.7 (Note)
X1228V14I-2.7
X1228V14IZ-2.7 (Note)
PART
MARKING
X1228S AL
X1228S ZAL
X1228S AM
X1228S ZAM
X1228V AL
X1228V ZAL
X1228V AM
X1228V ZAM
X1228S
X1228S Z
X1228S I
X1228S ZI
X1228V
X1228V Z
X1228V I
X1228V ZI
X1228S AN
X1228S ZAN
X1228S AP
X1228S ZAP
X1228V AN
X1228V ZAN
X1228V AP
X1228V ZAP
X1228S F
X1228S ZF
X1228S G
X1228S ZG
X1228V F
X1228V ZF
X1228V G
X1228V ZG
2.65V ± 100mV
2.85V ± 100mV
4.38V ± 112mV
V
CC
RANGE
(V)
2.7 to 5.5
V
TRIP
4.63V ± 112mV
TEMP RANGE
(°C)
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
0 to 70
0 to 70
-40 to 85
-40 to 85
PACKAGE
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb_free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld SOIC
14 Ld SOIC (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
14 Ld TSSOP
14 Ld TSSOP (Pb-free)
PKG. DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M14.173
M14.173
M14.173
M14.173
MDP0027
MDP0027
MDP0027
MDP0027
M14.173
M14.173
M14.173
M14.173
MDP0027
MDP0027
MDP0027
MDP0027
M14.173
M14.173
M14.173
M14.173
MDP0027
MDP0027
MDP0027
MDP0027
M14.173
M14.173
M14.173
M14.173
*Add "T1" suffix for tape and reel.
Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8100 Rev 4.00
May 18, 2006
Page 2 of 29
X1228
PIN DESCRIPTIONS
14 Ld TSSOP/SOIC
X1
X2
NC
NC
NC
RESET
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
V
BACK
PHZ/IRQ
NC
NC
SCL
SDA
NC = No internal connection
PIN ASSIGNMENTS
Pin Number
SOIC/TSSOP
1
Symbol
X1
Brief Description
X1.
The X1 pin is the input of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X1 are highly
recommended. See Application section for more recommendations.
X2.
The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz crystal
is used with the X1228 to supply a timebase for the real time clock. The recommended crystal
is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the placement of the crystal and the layout
of the circuit. Plenty of ground plane around the device and short traces to X2 are highly
recommended. See Application section for more recommendations.
RESET Output – RESET.
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has dropped below
a fixed V
TRIP
threshold. It is an open drain active LOW output. Recommended value for the
pullup resistor is 5k. If unused, tie to ground.
V
SS
.
Serial Data (SDA).
SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or open
collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls the
fall time of the output signal with the use of a slope controlled pull-down. The circuit is
designed for 400kHz 2-wire interface speeds.
Serial Clock (SCL).
The SCL input is used to clock all data into and out of the device. The
input buffer on this pin is always active (not gated).
Programmable Frequency/Interrupt Output – PHZ/IRQ.
This is either an output from the
internal oscillator or an interrupt signal output. It is a CMOS output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz, 1Hz
or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of the
Clock Control Memory map. See “Programmable Frequency Output Bits—FO1, FO0” on
page 14.
V
BACK
.
This input provides a backup supply voltage to the device. V
BACK
supplies power
to the device in the event the V
CC
supply fails. This pin can be connected to a battery, a
Supercap or tied to ground if not used.
V
CC
.
2
X2
6
RESET
7
8
V
SS
SDA
9
12
SCL
PHZ/IRQ
13
V
BACK
V
CC
14
FN8100 Rev 4.00
May 18, 2006
Page 3 of 29
X1228
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Voltage on V
CC
, V
BACK
and PHZ/IRQ
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V
CC
or V
BACK
(whichever is higher)
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) .............. 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
DC OPERATING CHARACTERISTICS
(Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
V
CC
V
BACK
V
CB
V
BC
Parameter
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
Conditions
Min
2.7
1.8
V
BACK
-0.2
V
BACK
Typ
Max
5.5
5.5
V
BACK
-0.1
V
BACK
+0.2
Unit
V
V
V
V
Notes
OPERATING CHARACTERISTICS
Symbol
I
CC1
I
CC2
I
CC3
Parameter
Read Active Supply
Current
Program Supply Current
(nonvolatile)
Main Timekeeping
Current
Timekeeping Current –
(Low Voltage Sense and
Watchdog Timer
disabled
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Schmitt Trigger Input
Hysteresis
Output LOW Voltage for
SDA and RESET
Output LOW Voltage for
PHZ/IRQ
Output HIGH Voltage for
PHZ/IRQ
Conditions
V
CC
= 2.7V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
CC
= 2.7V
V
CC
= 5.0V
V
BACK
= 1.8V
V
BACK
= 3.3V
Min
Typ
Max
400
800
2.5
3.0
10
20
Unit
µA
µA
mA
mA
µA
µA
µA
µA
Notes
1, 5, 7, 14
2, 5, 7, 14
3, 7, 8, 14, 15
3, 6, 9, 14, 15
“See Perfor-
mance Data”
1.25
1.5
10
10
-0.5
V
CC
x 0.7 or
V
BACK
x 0.7
V
CC
x 0.2 or
V
BACK
x 0.2
V
CC
+ 0.5 or
V
BACK
+ 0.5
I
BACK
I
LI
I
LO
V
IL
V
IH
V
HYS
V
OL1
V
OL2
V
OH2
µA
µA
V
V
V
10
10
13
13
13
11
11
12
V
CC
related level
V
CC
= 2.7V
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5.5V
.05 x V
CC
or
.05 x V
BACK
0.4
0.4
V
CC
x 0.3
V
CC
x 0.3
V
CC
x 0.7
V
CC
x 0.7
V
V
V
FN8100 Rev 4.00
May 18, 2006
Page 4 of 29
X1228
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
WC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; t
WC
after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) V
IL
= V
CC
x 0.1, V
IH
= V
CC
x 0.9, f
SCL
= 400kHz
(6) V
CC
= 0V
(7) V
BACK
= 0V
(8) V
SDA
= V
SCL
=V
CC
, Others = GND or V
CC
(9) V
SDA
=V
SCL
=V
BACK
, Others = GND or V
BACK
(10) V
SDA
= GND or V
CC
, V
SCL
= GND or V
CC
, V
RESET
= V
CC
or GND
(11) I
OL
= 3.0mA at 5.5V, 1.5mA at 2.7V
(12) I
OH
= -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for T
A
= 25°C
Capacitance
T
A
= 25°C, f = 1.0 MHz, V
CC
= 5V
Symbol
C
OUT(1)
C
IN(1)
Parameter
Output Capacitance (SDA, PHZ/IRQ, RESET)
Input Capacitance (SCL)
Max.
10
10
Units
pF
pF
Test Conditions
V
OUT
= 0V
V
IN
= 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Levels
Output Load
V
CC
x 0.1 to V
CC
x 0.9
10ns
V
CC
x 0.5
Standard Output Load
Figure 18. Standard Output Load for testing the device with V
CC
= 5.0V
Equivalent AC Output Load Circuit for V
CC
= 5V
5.0V
For V
OL
= 0.4V
and I
OL
= 3 mA
PHZ/IRQ
100pF
806
100pF
5.0V
1533
SDA
1316
FN8100 Rev 4.00
May 18, 2006
Page 5 of 29
