Clock OSC
SG3225VEN
SG3225VEN 27.000000 MHz CDGA
Product name
X1G0053510045xx
Product Number / Ordering code
Please refer to the 8.Packing information about xx (last 2 digits)
Output waveform
LVDS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 26 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.5
-55
-0.5
Typ.
-
-
-
Max.
+4
+125
Vcc+0.5
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST or OE Terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Disable current
Symmetry
Output voltage(LVDS)
Min.
-
3.135
-40
-25
-
-
-
45
250
-
1.15
-
-
70% Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ.
27.0000
3.3
-
-
-
-
-
50
350
-
1.25
-
100
-
-
-
-
-
339
-59.7
-93.5
-120.9
-140.9
-150.5
-157.2
-160
-
-
Max.
-
3.465
+85
+25
25
-
15
55
450
50
1.35
50
-
-
30% Vcc
0.3
0.3
10
-
-
-
-
-
-
-
-
-
-
Unit
MHz
V
ºC
x10
-6
mA
mA
mA
%
mV
mV
V
mV
Ω
Conditions / Remarks
-
-
-
OE=Vcc L_LVDS=100 ohm
-
OE=GND
At output crossing point
VOD1 , VOD2
| VOD1 - VOD2 |
VOS1 , VOS2
| VOS1 - VOS2 |
-
OE Terminal
OE Terminal
Output load condition(LVDS)
Input voltage
Rise time
Fall time
Start-up time
Phase jitter
Phase noise
f0
Vcc
T_use
f_tol
Icc
I_std
I_dis
SYM
V
OD
dV
OD
Vos
dVos
L_LVDS
V
IH
V
IL
t
r
tf
t_str
t
PJ
L(f)
ps
ps
ms
fs
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-6
At 20% to 80% output swing
At 20% to 80% output swing
-
Off set Frequency: 12kHz to 20MHz
Off set 1Hz
Off set 10Hz
Off set 100Hz
Off set 1kHz
Off set 10kHz
Off set 100kHz
Off set 1MHz
Frequency aging
f_age
x10 /Year
Included in Frequency tolerance 5 years
-
1 Page
3.Test circuit
1) To observe frequency and current
A
By-pass
capacitor 2
Vcc
Power
Supply
OE
OE pin
*1
NC
GND
1nF
By-pass
Capacitor1
1nF
Vcc
OUT
OUT
100Ω
50Ω
Frequency counter
2) To observe output wave
By-pass
capacitor 2
Vcc -1.25V
Power
Supply1
Vcc
OUT
OUT
Coaxial cable
Z0=50
Ω
OE
OE pin
*1
NC
GND
By-pass
capacitor
1
Oscilloscope
(50
Ω
termination)
-1.25 V
Power
supply2
*Each output line is same length
3) Measurement condition
A) Oscilloscope
•Bandwidth should be 5 times higher than DUT’s output frequency (2.5 GHz).
•Probe ground should be placed closely from test point and lead length should be as short as possible.
B) By-pass capacitor 1 (approx. 0.1 μF) places closely between Vcc and GND.
C) By-pass capacitor 2 (approx. 10 μF) places closely between power supply terminals on the board.
D) Use the current meter whose internal impedance value is small.
E) Power supply
• Start up time (0 Vg90 %Vcc) of power source should be more than 150 μs
• Impedance of power supply should be as low as possible.
2 Page
4.Timing chart
Output offset voltage
OUT
V
OS2
V
OS1
XOUT
dVOS=|VOS2-VOS1|
Differential output voltage
OUT
V
OD2
V
OD1
XOUT
dVOD=|VOD2-VOD1|
Duty
OUT
XOUT
tw
tout
SYM=tw/tout
×100(%)
Rise time / Fall time
0.8Vsw
0.8Vsw
Vsw
0V
OUT-XOUT
0.2Vsw
0.2Vsw
t
r
t
f
3 Page
5.External dimensions
(Unit: mm)
6.Footprint(Recommended)
(Unit: mm)
#6
#5
#4
#1
#2
#3
2.58
In order to achieve optimum jitter
performance, the 0.1 μF an7d 10 μF capacitor is required.
These capacitors should be placed as close
to Vcc (#6 pin) as possible. It is also recommended that the
capacitors are placed on the device side of the PCB.
7.Reflow profile
Reflow condition (Follow of JEDEC STD-020D.01)
Temperature [
C
]
300
250
200
150
100
50
Time +25
C
to Peak
0
60
120 180 240 300 360 420 480 540 600 660 720 780
Time [ s ]
TL
; +217
C
Ts max ; +200
C
Ts min ; +150
C
TP
; +260
C
+255
C
Avg. Ramp-up
3
C
/ s Max.
tp
; 20 s
tL
60 s to 150 s
( +217
C
over )
to 40 s
Ramp-down
6
C
/ s Max.
ts
60 s to 180 s
( +150
C
to +200
C
)
4 Page
1.85
1.05
0.82
0.86
9.Packing information
[ 1 ]Product number last 2 digits code(xx) description
The recommended code is "00"
Code
13
14
00
Condition
500pcs / Reel
1000pcs / Reel
2000pcs / Reel
X1G0053510045xx
Code
01
11
12
Condition
Any Q'ty vinyl bag(Tape cut)
Any Q'ty / Reel
250pcs / Reel
5 Page
