system wide reduction of EMI of all clock dependent
signals. The P2040C allows significant system cost
savings by reducing the number of circuit board layers and
shielding that are traditionally required to pass EMI
regulations.
The P2040C uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all-digital method. The
P2040C modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock and, more
importantly, decreases the
peak amplitudes of its
harmonics. This result in a significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The P2040C is targeted towards digital flat panel
applications for Notebook PCs, Palm-size PCs, Office
Automation Equipments and LCD Monitors.
Product Description
The P2040C is a selectable spread spectrum frequency
modulator designed specifically for digital flat panel
applications.
The
P2040C
reduces
electromagnetic
interference (EMI) at the clock source which provides
Block Diagram
SR0 SR1 MRA SSON#
VDD
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Alliance Semiconductor
2575 Augustine Drive
•
Santa Clara, CA
•
Tel: 408.855.4900
•
Fax: 408.855.4999
•
www.alsc.com
Notice: The information in this document is subject to change without notice.
September 2005
rev 1.4
Pin Configuration
CLKIN
MRA
SR1
VSS
1
2
8
7
P2040C
VDD
SR0
ModOUT
SSON#
P2040C
3
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
MRA
SR1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum
function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor.
Spread spectrum Clock Output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Power supply for the entire chip.
Modulation Selection (Commercial) – Table 1
MRA
0
0
0
0
1
1
1
1
SR1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range
54MHz
±1.4%
±2.0%
±1.1%
±1.8%
±1.3%
±2.2%
±1.4%
±2.1%
65MHz
±1.2%
±1.9%
±0.9%
±1.5%
±1.3%
±2.1%
±1.3%
±2.1%
81MHz
±1.0%
±1.6%
±0.5%
±1.0%
±1.3%
±2.1%
±1.4%
±2.1%
140MHz
±0.6%
±1.0%
±0.3%
±0.54%
±1.25%
±2.0%
±1.2%
±1.9%
162MHz
±0.4%
±0.8%
±0.3%
±0.4%
±1.1%
±1.8%
±0.9%
±1.4%
Modulation Rate
(Fin/80) * 62.49KHz
(Fin/80) * 62.49KHz
(Fin/80) * 62.49KHz
(Fin/80) * 62.49KHz
(Fin/80) * 20.83KHz
(Fin/80) * 20.83KHz
(Fin/80) * 20.83KHz
(Fin/80) * 20.83KHz
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 9
September 2005
rev 1.4
Spread Spectrum Selection
P2040C
Table 1 illustrates the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without
affecting system performance. The spreading is described as a percentage deviation of the center frequency
(Note: The center frequency is the frequency of the external reference input on CLKIN, Pin 1).
Example:
P2040C is designed for high resolution flat panel applications and is able to support panel frequencies from 50MHz
to 170MHz. For a 65MHz pixel clock frequency, a spreading selection of MRA=0, SR1=1 and SR0 =1 provides a percentage
deviation of ±1.50% (see Table 1). This result in frequency on ModOUT being swept from 64.03MHz to 65.98MHz at a
modulation rate of 50.77KHz (see Table 1). This particular example (see Figure below) given here is a common EMI reduction
method for notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic
accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
`
65MHz from graphics accelerator
1
CLKIN
MRA
SR1
VDD
8
SR0
7
ModOUT
SSON#
6
2
0.1µF
Modulated 65MHz signal with
±1.5 % deviation and modulation
rate of 50.77KHz. This signal is
connected back to the spread
+3.3V
spectrum input pin (SSIN) of the
graphics accelerator.
3
4 VSS
5
P2040C
Digital control for the SS enable
or disable
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 9
September 2005
rev 1.4
Absolute Maximum Ratings
Symbol
VDD, V
IN
T
STG
T
A
T
s
ө
JA
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Thermal Resistance from Junction For SOIC Package
to Ambient ( No Air Flow)
For TSSOP Package
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
P2040C
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
-20 to +85
260
156.5
124
150
2
Unit
V
°C
°C
°C
°C/W
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
VDD
t
ON
Z
OUT
Input low voltage
Input high voltage
Parameter
Min
VSS - 0.3
2.0
-
-
-
2.5
-
9
3.0
-
-
Typ
-
-
-
-
-
-
0.7
16
3.3
0.18
50
Max
0.8
VDD + 0.3
-40
40
0.4
-
-
22
3.6
-
-
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Ω
Input low current (pull-up resistor on inputs SR0, SR1 and MRA)
Input high current (pull-down resistor on input SSON#)
Output low voltage (VDD = 3.3V, I
OL
= 20mA)
Output high voltage (VDD = 3.3V, I
OL
= 20mA)
Static supply current standby mode
Dynamic supply current (3.3V and 10pF loading)
Operating Voltage
Power-up time (first locked cycle after power up)
Clock output impedance
AC Electrical Characteristics
Symbol
f
IN
t
LH
*
t
HL
*
t
JC
t
D
Input frequency
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
Parameter
Min
50
0.3
0.3
-
45
Typ
0.7
0.7
-
50
Max
170
1.0
1.0
360
55
Unit
MHz
nS
nS
pS
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 9
September 2005
rev 1.4
Package Information
8-lead (150-mil) SOIC Package
P2040C
E
H
D
A2
A
θ
e
B
A
1
C
L
D
Dimensions
Symbol
Min
A1
A
A2
B
C
D
E
e
H
L
θ
Inches
Max
0.010
0.069
0.059
0.020
0.010
0.004
0.053
0.049
0.012
0.007
Millimeters
Min
Max
0.10
1.35
1.25
0.31
0.18
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
0.41
0°
1.27
8°
0.25
1.75
1.50
0.51
0.25
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
0.016
0°
0.050
8°
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
