This X24042 device has been acquired by
IC MICROSYSTEMS from Xicor, Inc.
4K
Preliminary Information
TYPICAL FEATURES
X24042
Serial E PROM
DESCRIPTION
2
512 x 8 Bit
Pin 7 No Connect
2
•
2.7V to 5.5V Power Supply
•
Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
The X24042 is a CMOS 4,096 bit serial E PROM,
internally organized 512 x 8. The X24042 features a
serial interface and software protocol allowing operation on
a simple two wire bus.
The X24042 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
The X24042 utilizes Xicor’s proprietary Direct Write
providing a minimum endurance of 100,000 cycles
TM
•
Internally Organized 512 x 8
•
2 Wire Serial Interface
—Standby Current Less Than 50
∝
A
—Bidirectional Data Transfer Protocol
•
Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
•
Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
cell
and a minimum data retention of 100 years.
•
8 Pin Mini-DlP and 8 Pin SOIC Packages
FUNCTIONAL DIAGRAM
(8) V
CC
(4) V
SS
START CYCLE
H.V. GENERATION
TIMING
& CONTROL
(5) SDA
START
STOP
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
(6) SCL
(3) A 2
(2) A 1
(1) A 0
+COMPARATOR
LOAD
INC
XDEC
E PROM
32 X 128
2
WORD
ADDRESS
COUNTER
R/W
YDEC
8
CK
PIN
DATA REGISTER
D
OUT
D
OUT
ACK
3849 FHD F01
© Xicor, 1991 Patents Pending
3849-1
1
Characteristics subject to change without notice
X24042
PIN DESCRIPTIONS
Serial Clock (SCL)
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-Up
A
0
A
1
A
2
PIN CONFIGURATION
DIP/SOIC
1
2
3
4
X24042
8
7
6
5
V
CC
NC
V
SS
SCL
SDA
3849 FHD F02
Resistor selection graph at the end of this data sheet.
Address (A
0
)
A
0
is unused by the X24042, however, it must be tied to V
SS
to insure proper device operation.
Address (A
1
, A
2
)
The Address inputs are used to set the appropriate bits of
the seven bit slave address. These inputs can be used
static or actively driven. If used statically they must be
to V
SS
or V
CC
as appropriate. If driven they must be
tied
PIN NAMES
Symbol
A
0
–A
2
SDA
SCL
NC
V
SS
V
CC
Description
Address Inputs
Serial Data
Serial Clock
No Connect
Ground
Supply Voltage
3849 PGM T01
driven to V
SS
or to V
CC
.
2
X24042
DEVICE OPERATION
The X24042 supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device as
the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24042 will be considered a slave in all
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24042 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the
X24042 to place the device into the standby power mode
after a read sequence. A stop condition can only be
issued after the transmitting device has released the
applications.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
bus.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3849 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3849 FHD F07
3
X24042
after the receipt of each subsequent eight bit word.
In the read mode the X24042 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24042
will continue to transmit data. If an acknowledge is not
detected, the X24042 will terminate further data trans-
missions. The master must then issue a stop condition to
return the X24042 to the standby power mode and
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the
ninth clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data.
Refer to Figure 3.
The X24042 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been se-
lected, the X24042 will respond with an acknowledge
place the device into a known state.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3849 FHD F08
4
X24042
DEVICE ADDRESSING
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24042 this is fixed as
The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the X24042 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of the A2
and A1 inputs). Upon a correct compare the X24042
1010[B].
Figure 4. Slave Address
HIGH
ORDER
DEVICE TYPE
IDENTIFIER
WORD
ADDRESS
outputs an acknowledge on the SDA line. Depending on the
state of the R/W bit, the X24042 will execute a read
or write operation.
WRITE OPERATIONS
1
0
1
0
A2
A1
A0
R/W
DEVICE
ADDRESS
Byte Write
For a write operation, the X24042 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
512 words in the selected page of memory. Upon
receipt of the word address the X24042 responds with an
acknowledge, and awaits the next eight bits of data,
again responding with an acknowledge. The master
then terminates the transfer by generating a stop condi-
tion, at which time the X24042 begins the internal write
cycle to the nonvolatile memory. While the internal write
cycle is in progress the X24042 inputs are disabled, and the
device will not respond to any requests from the
master. Refer to Figure 5 for the address, acknowledge
and data transfer sequence.
3849 FHD F09
The next two significant bits addresses a particular
device. A system could have up to four X24042 devices
on the bus (see Figure 10). The four addresses are
defined by the state of the A1 and A2 input.
The next bit of the slave address is an extension of the
array’s address and is concatenated with the eight bits
of address in the word address field, providing direct
access to the whole 512 x 8 array.
Figure 5. Byte Write
S
T
BUS ACTIVITY:
MASTER
A
R
SLAVE
ADDRESS
WORD
ADDRESS
DATA
S
T
O
P
T
S
A
C
A
C
A
C
SDA LINE
BUS ACTIVITY:
X24042
P
K
K
K
3849 FHD F10
5
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