A
PPLICATION
N
OTE
A V A I L A B L E
X25080
8K
AN61
X25080
SPI Serial E
2
PROM With Block Lock
TM
Protection
DESCRIPTION
1K x 8 Bit
FEATURES
• 2MHz Clock Rate
• SPI Modes (0,0 & 1,1)
• 1K X 8 Bits
— 32 Byte Page Mode
• Low Power CMOS
— <1
µ
A Standby Current
— <5mA Active Current
• 2.7V To 5.5V Power Supply
• Block Lock Protection
— Protect 1/4, 1/2 or all of E
2
PROM Array
• Built-in Inadvertent Write Protection
— Power-Up/Power-Down protection circuitry
— Write Enable Latch
— Write Protect Pin
• Self-Timed Write Cycle
— 5ms Write Cycle Time (Typical)
• High Reliability
— Endurance: 100,000 cycles
— Data Retention: 100 Years
— ESD protection: 2000V on all pins
• 8-Lead PDlP Package
• 8-Lead SOIC Package
• 14-Lead TSSOP Package
FUNCTIONAL DIAGRAM
STATUS
REGISTER
WRITE
PROTECT
LOGIC
The X25080 is a CMOS 8192-bit serial E
2
PROM,
internally organized as 1K x 8. The X25080 features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple three-wire bus. The bus
signals are a clock input (SCK) plus separate data in (SI)
and data out (SO) lines. Access to the device is con-
trolled through a chip select (CS) input, allowing any
number of devices to share the same bus.
The X25080 also features two additional inputs that
provide the end user with added flexibility. By asserting
the
HOLD
input, the X25080 will ignore transitions on its
inputs, thus allowing the host to service higher priority
interrupts. The
WP
input can be used as a hardwire input
to the X25080 disabling all write attempts to the status
register, thus providing a mechanism for limiting end
user capability of altering 0, 1/4, 1/2 or all of the memory.
The X25080 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
X DECODE
LOGIC
8
1K BYTE
ARRAY
8 X 256
SO
SI
SCK
CS
HOLD
COMMAND
DECODE
AND
CONTROL
LOGIC
8
8 X 256
16
16 X 256
WP
WRITE
CONTROL
AND
TIMING
LOGIC
32
8
Y DECODE
DATA REGISTER
3090 ILL F01
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3090-1.7 6/11/96 T3/C1/D0 NS
1
Characteristics subject to change without notice
X25080
PIN DESCRIPTIONS
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock
input, while data on the SO pin change after the falling
edge of the clock input.
Chip Select (CS)
When
CS
is HIGH, the X25080 is deselected and the SO
output pin is at high impedance and unless an internal
write operation is underway, the X25080 will be in the
standby power mode.
CS
LOW enables the X25080,
placing it in the active power mode. It should be noted
that after power-up, a HIGH to LOW transition on
CS
is
required prior to the start of any operation.
Write Protect (WP)
When
WP
is LOW and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the X25080 status register are
disabled, but the part otherwise functions normally.
When
WP
is held HIGH, all functions, including nonvola-
tile writes operate normally.
WP
going LOW while
CS
is
still LOW will interrupt a write to the X25080 status
register. If the internal write cycle has already been
initiated,
WP
going LOW will have no effect on a write.
The
WP
pin function is blocked when the WPEN bit in
the status register is “0”. This allows the user to install the
X25080 in a system with
WP
pin grounded and still be
able to write to the status register. The
WP
pin functions
will be enabled when the WPEN bit is set “1”.
Hold (HOLD)
HOLD
is used in conjunction with the
CS
pin to select the
device. Once the part is selected and a serial sequence
is underway,
HOLD
may be used to pause the serial
communication with the controller without resetting the
serial sequence. To pause,
HOLD
must be brought
LOW while SCK is LOW. To resume communication,
HOLD
is brought HIGH, again while SCK is LOW. If the
pause feature is not used,
HOLD
should be held HIGH
at all times.
PIN CONFIGURATION
DIP/SOIC
CS
SO
WP
VSS
1
2
3
4
X25080
8
7
6
5
VCC
HOLD
SCK
SI
TSSOP
CS
SO
NC
NC
NC
WP
VSS
1
2
3
4
5
6
7
14
13
12
X25080
11
10
9
8
VCC
HOLD
NC
NC
NC
SCK
SI
3090 ILL F02.2
PIN NAMES
SYMBOL
CS
SO
SI
SCK
WP
V
SS
V
CC
HOLD
NC
DESCRIPTION
Chip Select Input
Serial Output
Serial Input
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Hold Input
No Connect
3090 PGM T01
2
X25080
PRINCIPLES OF OPERATION
The X25080 is a 1K x 8 E
2
PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25080 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising SCK.
CS
must be LOW and the
HOLD
and
WP
inputs must be HIGH during the entire operation. The
WP
input is “Don’t Care” if WPEN is set “0”.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
Data input is sampled on the first rising edge of SCK after
CS
goes LOW. SCK is static, allowing the user to stop
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
user can assert the
HOLD
input to place the X25080 into
a “PAUSE” condition. After releasing
HOLD,
the X25080
will resume operation from the point when
HOLD
was
first asserted.
Write Enable Latch
The X25080 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte, page, or status register write
cycle.
Status Register
The RDSR instruction provides access to the status
register. The status register may be read at any time,
even during a write cycle. The status register is format-
ted as follows:
7
6
WPEN X
5
X
4
X
3
BP1
2
BP0
1
WEL
0
WIP
3090 PGM T02
WPEN, BP0 and BP1 are set by the WRSR instruction.
WEL and WIP are read-only and automatically set by
other operations.
The Write-In-Process (WIP) bit indicates whether the
X25080 is busy with a write operation. When set to a “1”,
a write is in progress, when set to a “0”, no write is in
progress. During a write, all other bits are set to “1”.
The Write Enable Latch (WEL) bit indicates the status of
the “write enable” latch. When set to a “1”, the latch is set,
when set to a “0”, the latch is reset.
The Block Protect (BP0 and BP1) bits are nonvolatile
and allow the user to select one of four levels of protec-
tion. The X25080 is divided into four 2048-bit segments.
One, two, or all four of the segments may be protected.
That is, the user may read the segments but will be
unable to alter (write) data within the selected segments.
The partitioning is controlled as illustrated below.
Status Register Bits
BP1
BP0
0
0
1
1
0
1
0
1
Array Addresses
Protected
None
$0300–$03FF
$0200–$03FF
$0000–$03FF
3090 PGM T03
Table 1. Instruction Set
Instruction Name
WREN
WRDI
RDSR
WRSR
READ
WRITE
Instruction Format*
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
Write Status Register
Read Data from Memory Array beginning at selected
address
Write Data to Memory Array beginning at Selected Address
(1 to 32 Bytes)
3090 PGM T04
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25080
Write-Protect Enable
The Write-Protect-Enable (WPEN) is available for the
X25080 as a nonvolatile enable bit for the
WP
pin.
Protected Unprotected Status
WPEN
WP
WEL Blocks
Blocks
Register
0
0
1
1
X
X
X
X
LOW
LOW
HIGH
HIGH
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Protected
Protected
Writable
3090 PGM T05.1
To read the status register the
CS
line is first pulled LOW
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
status register are shifted out on the SO line. The read
status register sequence is illustrated in Figure 2.
Write Sequence
Prior to any attempt to write data into the X25080, the
“write enable” latch must first be set by issuing the
WREN instruction (See Figure 3).
CS
is first taken LOW,
then the WREN instruction is clocked into the X25080.
After all eight bits of the instruction are transmitted,
CS
must then be taken HIGH. If the user continues the write
operation without taking
CS
HIGH after issuing the
WREN instruction, the write operation will be ignored.
To write data to the E
2
PROM memory array, the user
issues the WRITE instruction, followed by the address
and then the data to be written. This is minimally a thirty-
two clock operation.
CS
must go LOW and remain LOW
for the duration of the operation. The host may continue
to write up to 32 bytes of data to the X25080. The only
restriction is the 32 bytes must reside on the same page.
If the address counter reaches the end of the page and
the clock continues, the counter will “roll over” to the first
address of the page and overwrite any data that may
have been written.
For the write operation (byte or page write) to be
completed,
CS
can only be brought HIGH after bit 0 of
data byte N is clocked in. If it is brought HIGH at any other
time the write operation will not be completed. Refer to
Figures 4 and 5 below for a detailed illustration of the
write sequences and time frames in which
CS
going
HIGH are valid.
To write to the status register, the WRSR instruction is
followed by the data to be written. Data bits 0, 1, 4, 5 and
6 must be “0”. Figure 6 shows this sequence.
While the write is in progress following a status register or
E
2
PROM write sequence, the status register may be read
to check the WIP bit. During this time the WIP bit will be “1”.
Hold Operation
The
HOLD
input should be HIGH (at V
IH
) under normal
operation. If a data transfer is to be interrupted
HOLD
can be pulled LOW to suspend the transfer until it can be
resumed. The only restriction is the SCK input must be
LOW when
HOLD
is first pulled LOW and SCK must also
be LOW when
HOLD
is released.
The
HOLD
input may be tied HIGH either directly to V
CC
or tied to V
CC
through a resistor.
4
The Write Protect (WP) pin and the nonvolatile Write
Protect Enable (WPEN) bit in the Status Register control
the programmable hardware write protect feature. Hard-
ware write protection is enabled when
WP
pin is LOW,
and the WPEN bit is “1”. Hardware write protection is
disabled when either the
WP
pin is HIGH or the WPEN
bit is “0”. When the chip is hardware write protected,
nonvolatile writes are disabled to the Status Register,
including the Block Protect bits and the WPEN bit itself,
as well as the block-protected sections in the memory
array. Only the sections of the memory array that are not
block-protected can be written.
Note:
Since the WPEN bit is write protected, it
cannot be changed back to a “0”, as long as
the
WP
pin is held LOW.
Clock and Data Timing
Data input on the SI line is latched on the rising edge of
SCK. Data is output on the SO line by the falling edge of
SCK.
Read Sequence
When reading from the E
2
PROM memory array
CS
is
first pulled LOW to select the device. The 8-bit READ
instruction is transmitted to the X25080, followed by the
16-bit address of which the last 10 are used. After the
READ opcode and address are sent, the data stored in
the memory at the selected address is shifted out on the
SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock
pulses. The address is automatically incremented to the
next higher address after each byte of data is shifted out.
When the highest address is reached ($03FF) the
address counter rolls over to address $0000 allowing
the read cycle to be continued indefinitely. The read
operation is terminated by taking
CS
HIGH. Refer to the
read E
2
PROM array operation sequence illustrated in
Figure 1.
X25080
Operational Notes
The X25080 powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on
CS
is required to
enter an active state and receive an instruction.
• SO pin is high impedance.
• The “write enable” latch is reset.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A WREN instruction must be issued to set the “write
enable” latch.
•
CS
must come HIGH at the proper clock count in
order to start a write cycle.
Figure 1. Read E
2
PROM Array Operation Sequence
CS
0
SCK
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
INSTRUCTION
SI
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
SO
7
MSB
6
5
4
3
2
1
0
3090 ILL F03
Figure 2. Read Status Register Operation Sequence
CS
0
SCK
1
2
3
4
5
6
7
8
9
10 11 12 13 14
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
7
MSB
6
5
4
3
2
1
0
3090 ILL F04
5
PCB设计
