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PPLICATION

OTE

A V A I L A B L E

AN61 • AN75 • AN77 • AN79 • AN82

X25F064/032/016/008

SerialFlash™ Memory With Block Lock

Protection

FEATURES

• 1MHz Clock Rate

• SPI Serial Interface

• 64K/32K/16K/8K Bits

— 32 Byte Small Sector Program Mode

• Low Power CMOS

— <1

A Standby Current

— <5mA Active Current

• 1.8V – 3.6V or 5V “Univolt” Read and

Program Power Supply Versions

• Block Lock Protection

— Protect 1/4, 1/2, or all of E

PROM Array

• Built-in Inadvertent Program Protection

— Power-Up/Power-Down protection circuitry

— Program Enable Latch

— Program Protect Pin

• Self-Timed Program Cycle

— 5ms Program Cycle Time (Typical)

• High Reliability

— Endurance: 100,000 cycles per byte

— Data Retention: 100 Years

— ESD protection: 2000V on all pins

• 8-Lead PDlP Package

• 8-Lead 150 mil SOIC Packages

• 32K, 16K, 8K available in 14-Lead TSSOP,

64K available in 20-Lead TSSOP

FUNCTIONAL DIAGRAM

DATA REGISTER

SECTOR DECODE LOGIC

COMMAND

DECODE

AND CONTROL

LOGIC

DECODE

LOGIC

DESCRIPTION

The X25F064/032/016/008 family are 8/16/32/64K-bit

CMOS SerialFlash memory, internally organized

X 8. They feature a “Univolt” Program and Read voltage,

Serial Peripheral Interface (SPI), and software protocol

allowing operation on a simple three-wire bus. The bus

signals are a clock input (SCK), plus separate data in

(SI) and data out (SO) lines. Access to the device is

controlled through a chip select (CS) input, allowing any

number of devices to share the same bus.

The X25F064/032/016/008 also features two additional

inputs that provide the end user with added flexibility. By

asserting the

HOLD

input, the X25F064/032/016/008

will ignore transitions on its inputs, thus allowing the host

to service higher priority interrupts. The

input can be

used as a hardwire input to the X25F064/032/016/008

disabling all program attempts to the status register,

thus providing a mechanism for limiting end user capa-

bility of altering 0, 1/4, 1/2, or all of the memory.

The X25F064/032/016/008 utilizes Xicor’s proprietary

flash cell, providing a minimum endurance

of 100,000 cycles and a minimum data retention of

100 years.

SCK

MEMORY

ARRAY

HOLD

STATUS

PROGRAMMING

CONTROL LOGIC

HIGH VOLTAGE

CONTROL

6685 ILL F01.4

SerialFlash™ and Block Lock™ Protection are trademarks of Xicor, Inc.

6685-3.1 8/29/96 T3/C0/D0 SH

Characteristics subject to change without notice

X25F064/032/016/008

PIN DESCRIPTIONS

Serial Output (SO)

SO is a push-pull serial data output pin. During a read

cycle, data is shifted out on this pin. Data is clocked out

by the falling edge of the serial clock.

Serial Input (SI)

SI is the serial data input pin. All opcodes, byte

addresses, and data to be written to the memory are

input on this pin. Data is latched by the rising edge of the

serial clock.

Serial Clock (SCK)

The Serial Clock controls the serial bus timing for data

input and output. Opcodes, addresses, or data present

on the SI pin are latched on the rising edge of the clock

input, while data on the SO pin change after the falling

edge of the clock input.

Chip Select (CS)

When

is HIGH, the X25F064/032/016/008 is

deselected and the SO output pin is at high impedance

and unless an internal program operation is underway

the X25F064/032/016/008 will be in the standby power

mode.

LOW enables the X25F064/032/016/008,

placing it in the active power mode. It should be noted

that after power-up, a HIGH to LOW transition on

required prior to the start of any operation.

Program Protect (PP)

When

is LOW and the nonvolatile bit PPEN is “1”,

nonvolatile programming of the X25F064/032/016/008

status register is disabled, but the part otherwise func-

tions normally. When

is held HIGH, all functions,

including nonvolatile programming operate normally.

going LOW while

is still LOW will interrupt

programming of the X25F064/032/016/008 status regis-

ter. If the internal program cycle has already been

initiated,

going LOW will have no effect on program-

ming.

The

pin function is blocked when the PPEN bit in

the status register is “0”. This allows the user to install the

X25F064/032/016/008 into a system with

grounded and still be able to program the status register.

The

pin functions will be enabled when the PPEN bit

is set “0”.

VSS

Hold (HOLD)

HOLD

is used in conjunction with the

pin to select the

device. Once the part is selected and a serial sequence

is underway,

HOLD

may be used to pause the serial

communication with the controller without resetting the

serial sequence. To pause,

HOLD

must be brought

LOW while SCK is LOW. To resume communication,

HOLD

is brought HIGH, again while SCK is LOW. If the

pause feature is not used,

HOLD

should be held HIGH

at all times.

PIN CONFIGURATION

8-Lead DIP/SOIC

VSS

14-Lead TSSOP

VCC

HOLD

SCK

VSS

VCC

HOLD

SCK

20-Lead TSSOP

X25F064

VCC

HOLD

SCK

X25F064/

032/016/

008

X25F032/

016/008

6685 ILL F02.4

PIN NAMES

SYMBOL

SCK

HOLD

DESCRIPTION

Chip Select Input

Serial Output

Serial Input

Serial Clock Input

Program Protect Input

Ground

Supply Voltage

Hold Input

No Connect

6685 PGM T01.1

X25F064/032/016/008

PRINCIPLES OF OPERATION

The X25F064/032/016/008 family are SerialFlash

Memory designed to interface directly with the synchro-

nous serial peripheral interface (SPI) of many popular

microcontroller families.

The X25F064/032/016/008 family contains an 8-bit

instruction register. It is accessed via the SI input, with

data being clocked in on the rising SCK.

must be

LOW and the

HOLD

and

inputs must be HIGH during

the entire operation. The

input is “Don’t Care” if

PPEN is set “0”.

Table 1 contains a list of the instructions and their

operation codes. All instructions, addresses and data

are transferred MSB first.

Data input is sampled on the first rising edge of SCK after

goes LOW. SCK is static, allowing the user to stop

the clock and then resume operations. If the clock line is

shared with other peripheral devices on the SPI bus, the

user can assert the

HOLD

input to place the X25F064/

032/016/008 into a “PAUSE” condition. After

releasing

HOLD,

the X25F064/032/016/008 device will

resume operation from the point when

HOLD

was first

asserted.

Program Enable Latch

The X25F064/032/016/008 device contains a

program enable latch. This latch must be SET before a

program operation will be completed internally. The

PREN instruction will set the latch and the PRDI

instruction will reset the latch. This latch is automatically

reset on power-up and after the completion of a sector

program or status register write cycle.

Status Register

The RDSR instruction provides access to the status

even during a program cycle. The status register is

Table 1. Instruction Set

Instruction Name

PREN

PRDI

RDSR

PRSR

READ

PROGRAM

Instruction Format*

0000 0110

0000 0100

0000 0101

0000 0001

0000 0011

0000 0010

Operation

Set the Program Enable Latch (Enable Program Operations)

Reset the Program Enable Latch (Disable Program Operations)

Read Status Register

Program Status Register

Read from Memory Array beginning at Selected Address

Program Memory Array beginning at Selected Address

(32 Bytes)

6685 PGM T04.2

formatted as follows:

PPEN

BL1

BL0

PEL

PIP

6685 PGM T02.2

PPEN, BL0, and BL1 are set by the PRSR instruction.

PEL and PIP are “read-only” and automatically set by

other operations.

The Programming-In-Process (PIP) bit indicates

whether the X25F064/032/016/008 device is busy

with a program operation. When set to a “1”

programming is in progress, when set to a “0” no

programming is in progress. During programming, all

other bits are set to “1”.

The Program Enable Latch (PEL) bit indicates the

status of the program enable latch. When set to a “1” the

latch is set; when set to a “0” the latch is reset.

The Block Lock (BL0 and BL1) bits are nonvolatile and

allow the user to select one of four levels of protection.

The X25F064/032/016/008 device array is divided into

four equal segments. One, two, or all four of the seg-

ments may be locked. That is, the user may read the

segments, but will be unable to alter (program) data

within the selected segments. The partitioning is con-

trolled as illustrated below.

Status Register Bits

BL1

BL0

Array Addresses

Locked

None

upper fourth

upper half

All

6685 PGM T03.1

Program-Protect Enable

The Program-Protect-Enable bit (PPEN) in the

X25F064/032/016/008 status register acts as an

enable bit for the

pin.

*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

X25F064/032/016/008

Locked

PEL Blocks

Unlocked

Blocks

Status

PPEN

LOW

HIGH

Locked

Locked Programmable Programmable

Locked

Locked Programmable

Locked

Locked Programmable Programmable

6685 PGM T05.2

tion. After the read status register opcode is sent, the

contents of the status register are shifted out on the SO

line. The Read Status Register Sequence is illustrated

in Figure 2.

Programming Sequence

Prior to any attempt to program the X25F064/032/016/

008 device, the program enable latch must first be set by

issuing the PREN instruction (See Figure 3).

is first

taken LOW, then the PREN instruction is clocked into

the X25F064/032/016/008 device. After all eight bits of

the instruction are transmitted,

must then be taken

HIGH. If the user continues the programming operation

without taking

HIGH after issuing the PREN instruc-

tion, the programming operation will be ignored.

To program the SerialFlash memory array, the user

issues the PROGRAM instruction, followed by the ad-

dress of the first location in the sector and then the data

to be programmed. The data is programmed in a 256-

clock operation.

must go LOW and remain LOW for

the duration of the operation. The 32 bytes must reside

in the same sector and cannot cross sector boundaries.

If the address counter reaches the end of the sector

and the clock continues, or if fewer than 32 bytes are

clocked in, the contents of the sector cannot be guaranteed.

For the program operation to be completed,

can only

be brought HIGH after bit 0 of data byte 32 is clocked in.

If it is brought HIGH at any other time the program

operation will not be completed. Refer to Figure 4 below

for a detailed illustration of the programming sequence

and time frames in which

going HIGH is valid.

To program the status register, the PRSR instruction is

followed by the data to be programmed. Data bits 0, 1,

4, 5 and 6 must be “0”. This sequence is shown in Figure 5.

While the program cycle is in progress, following a

status register or memory write sequence, the status

time the PIP bit will be HIGH.

Hold Operation

The

HOLD

input should be HIGH (at V

) under normal

operation. If a data transfer is to be interrupted

HOLD

can be pulled LOW to suspend the transfer until it can be

resumed. The only restriction is that the SCK input

must be LOW when

HOLD

is first pulled LOW and SCK

must also be LOW when

HOLD

is released.

The

HOLD

input may be tied HIGH either directly to V

or tied to V

through a resistor.

The Program Protect (PP) pin and the nonvolatile

Program Protect Enable (PPEN) bit in the Status Reg-

ister control the programmable hardware write protect

feature. Hardware program protection is enabled when

pin is LOW, and the PPEN bit is “1”. Hardware

program protection is disabled when either the

pin is

HIGH or the PPEN bit is “0”. When the chip is hardware

program protected, nonvolatile programming of the Sta-

tus Register in disabled, including the Block Lock bits

and the PPEN bit itself, as well as the Block Lock

sections in the memory array. Only the sections of the

memory array that are not Block Locked can be pro-

grammed.

Note:

Since the PPEN bit is program protected, it

cannot be changed back to a “0”, as long as

the

pin is held LOW.

Clock and Data Timing

Data input on the SI line is latched on the rising edge of

SCK. Data is output on the SO line by the falling edge of

SCK.

Read Sequence

When reading from the SerialFlash memory array,

first pulled LOW to select the device. The 8-bit READ

instruction is transmitted to the X25F064/032/016/008

device, followed by the 16-bit address. After the read

opcode and address are sent, the data stored in the

memory at the selected address is shifted out on the SO

line. The data stored in memory at the next address can

be read sequentially by continuing to provide clock

pulses. The address is automatically incremented to the

next higher address after each byte of data is shifted out.

When the highest address is reached the address

counter rolls over to address $0000, allowing the read

cycle to be continued indefinitely. The read operation is

terminated by taking

HIGH. Refer to the Read

SerialFlash Memory Array Operation Sequence illustrated

in Figure 1.

To read the status register, the

line is first pulled

LOW to select the device followed by the 8-bit instruc-

X25F064/032/016/008

Operational Notes

The device powers-up in the following state:

• The device is in the low power standby state.

• A HIGH to LOW transition on

is required to

enter an active state and receive an instruction.

• SO pin is high impedance.

• The program enable latch is reset.

Data Protection

The following circuitry has been included to prevent

inadvertent programming:

• The program enable latch is reset upon power-up.

• A program enable instruction must be issued to set

the program enable latch.

•

must come HIGH at the proper clock count in

order to start a program cycle.

Figure 1. Read SerialFlash Memory Array Operation Sequence

SCK

20 21 22 23 24 25 26 27 28 29 30

INSTRUCTION

16 BIT ADDRESS

15 14 13

DATA OUT

HIGH IMPEDANCE

MSB

6685 ILL F03

Figure 2. Read Status Register Operation Sequence

SCK

10 11 12 13 14

INSTRUCTION

DATA OUT

HIGH IMPEDANCE

MSB

6685 ILL F04