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X28C64

64K

X28C64

5 Volt, Byte Alterable E

PROM

DESCRIPTION

8K x 8 Bit

FEATURES

•

150ns Access Time

Simple Byte and Page Write

—Single 5V Supply

—No External High Voltages or V

Control

Circuits

—Self-Timed

—No Erase Before Write

—No Complex Programming Algorithms

—No Overerase Problem

Low Power CMOS

—60mA Active Current Max.

—200

A Standby Current Max.

Fast Write Cycle Times

—64 Byte Page Write Operation

—Byte or Page Write Cycle: 5ms Typical

—Complete Memory Rewrite: 0.625 sec. Typical

—Effective Byte Write Cycle Time: 78

s Typical

Software Data Protection

End of Write Detection

—DATA Polling

—Toggle Bit

High Reliability

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

JEDEC Approved Byte-Wide Pinout

The X28C64 is an 8K x 8 E

PROM, fabricated with

Xicor’s proprietary, high performance, floating gate

CMOS technology. Like all Xicor programmable non-

volatile memories the X28C64 is a 5V only device. The

X28C64 features the JEDEC approved pinout for byte-

wide memories, compatible with industry standard RAMs.

The X28C64 supports a 64-byte page write operation,

effectively providing a 78µs/byte write cycle and en-

abling the entire memory to be typically written in 0.625

seconds. The X28C64 also features

DATA

and Toggle

Bit Polling, a system software support scheme used to

indicate the early completion of a write cycle. In addi-

tion, the X28C64 includes a user-optional software data

protection mode that further enhances Xicor’s hard-

ware write protect capability.

Xicor E

PROMs are designed and tested for applica-

tions requiring extended endurance. Inherent data re-

tention is greater than 100 years.

PIN CONFIGURATION

PLASTIC DIP

CERDIP

FLAT PACK

SOIC

A12

I/O0

I/O1

I/O2

VSS

X28C64

VCC

A11

A10

I/O7

I/O6

I/O5

I/04

I/O3

I/O0

X28C64

A11

A10

I/O7

I/O6

LCC

PLCC

VCC

A12

TSOP

I/O0

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

I/O6

I/O7

A10

A12

VCC

A11

1 32 31 30

X28C64

14 15 16 17 18 19 20

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

3853 ILL F23.1

3853 FHD F03

3853 FHD F02

3853-2.7 4/2/96 T0/C3/D2 NS

Characteristics subject to change without notice

X28C64

PIN DESCRIPTIONS

Addresses (A

–A

)

The Address inputs select an 8-bit memory location

during a read or write operation.

Chip Enable (CE)

The Chip Enable input must be LOW to enable all read/

write operations. When

is HIGH, power consumption

is reduced.

Output Enable (OE)

The Output Enable input controls the data output buffers

and is used to initiate read operations.

PIN NAMES

Symbol

–A

I/O

–I/O

FUNCTIONAL DIAGRAM

65,536-BIT

E2PROM

ARRAY

I/O1

I/O2

I/O3

I/O5

I/O6

I/O0

VSS

I/O4

I/O7

X28C64

A10

A11

Data In/Data Out (I/O

–I/O

)

Data is written to or read from the X28C64 through the

I/O pins.

Write Enable (WE)

The Write Enable input controls the writing of data to the

X28C64.

PIN CONFIGURATION

PGA

Description

Address Inputs

Data Input/Output

Write Enable

Chip Enable

Output Enable

+5V

Ground

No Connect

3853 PGM T01

A12

VCC

BOTTOM VIEW

3853 FHD F04

X BUFFERS

LATCHES AND

DECODER

A0–A12

ADDRESS

INPUTS

Y BUFFERS

LATCHES AND

DECODER

I/O BUFFERS

AND LATCHES

I/O0–I/O7

DATA INPUTS/OUTPUTS

VCC

VSS

3853 FHD F01

CONTROL

LOGIC AND

TIMING

X28C64

DEVICE OPERATION

Read

Read operations are initiated by both

and

LOW.

The read operation is terminated by either

returning HIGH. This two line control architecture elimi-

nates bus contention in a system environment. The data

bus will be in a high impedance state when either

is HIGH.

Write

Write operations are initiated when both

and

are

LOW and

is HIGH. The X28C64 supports both a

and

controlled write cycle. That is, the address is

latched by the falling edge of either

WE,

whichever

occurs last. Similarly, the data is latched internally by the

rising edge of either

WE,

whichever occurs first.

A byte write operation, once initiated, will automatically

continue to completion, typically within 5ms.

Page Write Operation

The page write feature of the X28C64 allows the entire

memory to be written in 0.625 seconds. Page write

allows two to sixty-four bytes of data to be consecutively

written to the X28C64 prior to the commencement of the

internal programming cycle. The host can fetch data

from another device within the system during a page

write operation (change the source address), but the

page address (A

through A

) for each subsequent

valid write cycle to the part during this operation must be

the same as the initial page address.

The page write mode can be initiated during any write

operation. Following the initial byte write cycle, the host

can write an additional one to sixty-three bytes in the

same manner as the first byte was written. Each succes-

sive byte load cycle, started by the

HIGH to LOW

transition, must begin within 100µs of the falling edge of

the preceding

WE.

If a subsequent

HIGH to LOW

transition is not detected within 100µs, the internal

automatic programming cycle will commence. There is

no page write window limitation. Effectively the page

write window is infinitely wide, so long as the host

continues to access the device within the byte load cycle

time of 100µs.

Write Operation Status Bits

The X28C64 provides the user two write operation

status bits. These can be used to optimize a system

write cycle time. The status bits are mapped onto the

I/O bus as shown in Figure 1.

Figure 1. Status Bit Assignment

I/O

RESERVED

TOGGLE BIT

DATA POLLING

3853 FHD F11

DATA

Polling (I/O

)

The X28C64 features

DATA

Polling as a method to

indicate to the host system that the byte write or page

write cycle has completed.

DATA

Polling allows a simple

bit test operation to determine the status of the X28C64,

eliminating additional interrupt inputs or external hard-

ware. During the internal programming cycle, any at-

tempt to read the last byte written will produce the

complement of that data on I/O

(i.e. write data = 0xxx

xxxx, read data = 1xxx xxxx). Once the programming

cycle is complete, I/O

will reflect true data. Note: If the

X28C64 is in the protected state and an illegal write

operation is attempted

DATA

Polling will not operate.

Toggle Bit (I/O

)

The X28C64 also provides another method for deter-

mining when the internal write cycle is complete. During

the internal programming cycle I/O

will toggle from

HIGH to LOW and LOW to HIGH on subsequent

attempts to read the device. When the internal cycle is

complete the toggling will cease and the device will be

accessible for additional read or write operations.

X28C64

DATA

Polling I/O

Figure 2.

DATA

Polling Bus Sequence

LAST

WRITE

VIH

I/O7

HIGH Z

VOL

3853 FHD F12

VOH

X28C64

READY

A0–A12

Figure 3.

DATA

Polling Software Flow

DATA

Polling can effectively halve the time for writing to

the X28C64. The timing diagram in Figure 2 illustrates

the sequence of events on the bus. The software flow

diagram in Figure 3 illustrates one method of implement-

ing the routine.

WRITE DATA

WRITES

COMPLETE?

YES

SAVE LAST DATA

AND ADDRESS

READ LAST

ADDRESS

IO7

COMPARE?

YES

X28C64

READY

3853 FHD F13

X28C64

The Toggle Bit I/O

Figure 4. Toggle Bit Bus Sequence

LAST

WRITE

I/O6

VOH

VOL

HIGH Z

X28C64

READY

* Beginning and ending state of I/O6 will vary.

3853 FHD F14

Figure 5. Toggle Bit Software Flow

The Toggle Bit can eliminate the software housekeeping

chore of saving and fetching the last address and data

written to a device in order to implement

DATA

Polling.

This can be especially helpful in an array comprised of

multiple X28C64 memories that is frequently updated.

Toggle Bit Polling can also provide a method for status

checking in multiprocessor applications. The timing

diagram in Figure 4 illustrates the sequence of events on

the bus. The software flow diagram in Figure 5 illustrates

a method for polling the Toggle Bit.

LAST WRITE

LOAD ACCUM

FROM ADDR n

COMPARE

ACCUM WITH

ADDR n

COMPARE

OK?

YES

X28C64

READY

3853 FHD F15