X28HC256
256K
X28HC256
5 Volt, Byte Alterable E
2
PROM
DESCRIPTION
32K x 8 Bit
FEATURES
•
•
•
•
•
•
•
Access Time: 70ns
Simple Byte and Page Write
—Single 5V Supply
— No External High Voltages or V
PP
Control
Circuits
—Self-Timed
— No Erase Before Write
— No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 60mA
—Standby: 500
µ
A
Software Data Protection
—Protects Data Against System Level
Inadvertent Writes
High Speed Page Write Capability
Highly Reliable Direct Write
™
Cell
—Endurance: 100,000 Write Cycles
—Data Retention: 100 Years
Early End of Write Detection
—DATA Polling
—Toggle Bit Polling
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 E
2
PROM. It is fabricated with
Xicor’s proprietary, textured poly floating gate tech-
nology, providing a highly reliable 5 Volt only nonvolatile
memory.
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA
Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data
retention of 100 years.
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28HC256
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
X28HC256
A7
LCC
PLCC
VCC
A12
A14
A13
WE
NC
TSOP
4
3
2
1 32 31 30
29
28
27
26
25
24
23
22
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A12
A14
NC
VCC
NC
WE
A13
A8
A9
A11
OE
X28HC256
21
13
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3859 ILL F22
3859 FHD F03
3859 FHD F02
©Xicor, Inc. 1991, 1995 Patents Pending
3859-2.8 8/5/97 T1/C0/D0 EW
1
Characteristics subject to change without notice
X28HC256
PIN DESCRIPTIONS
Addresses (A
0
–A
14
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28HC256 through
the I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28HC256.
PIN NAMES
Symbol
A
0
–A
14
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
PIN CONFIGURATION
PGA
I/O1
I/O2
I/O3
I/O6
I/O5
12
13
15
18
17
I/O0
A0
11
10
A1
9
A3
7
A5
5
A6
4
A2
A4
A12
VSS
I/O4
I/O7
14
16
19
CE
20
OE
22
VCC
A9
28
24
A14
WE
27
A10
21
A11
23
A8
25
A13
26
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3859 PGM T01
8
6
2
3
A7
1
FUNCTIONAL DIAGRAM
X28HC256
(BOTTOM VIEW)
3859 FHD F04
X BUFFERS
LATCHES AND
DECODER
A0–A14
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
256K-BIT
E2PROM
ARRAY
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
VCC
VSS
3859 FHD F01
CONTROL
LOGIC AND
TIMING
3859 FHD F01
2
X28HC256
DEVICE OPERATION
Read
Read operations are initiated by both
OE
and
CE
LOW.
The read operation is terminated by either
CE
or
OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The data
bus will be in a high impedance state when either
OE
or
CE
is HIGH.
Write
Write operations are initiated when both
CE
and
WE
are
LOW and
OE
is HIGH. The X28HC256 supports both a
CE
and
WE
controlled write cycle. That is, the address
is latched by the falling edge of either
CE
or
WE,
whichever occurs last. Similarly, the data is latched
internally by the rising edge of either
CE
or
WE,
whichever occurs first. A byte write operation, once
initiated, will automatically continue to completion, typi-
cally within 3ms.
Page Write Operation
The page write feature of the X28HC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight bytes
of data to be consecutively written to the X28HC256
prior to the commencement of the internal programming
cycle. The host can fetch data from another device
within the system during a page write operation (change
the source address), but the page address (A
7
through
A
14
) for each subsequent valid write cycle to the part
during this operation must be the same as the initial
page address.
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by the
WE
HIGH to LOW transition, must begin within 100µs of
the falling edge of the preceding
WE.
If a subsequent
WE
HIGH to LOW transition is not detected within
100µs, the internal automatic programming cycle will
commence. There is no page write window limitation.
Effectively the page write window is infinitely wide, so
long as the host continues to access the device within
the byte load cycle time of 100µs.
Write Operation Status Bits
The X28HC256 provides the user two write operation
status bits. These can be used to optimize a system write
cycle time. The status bits are mapped onto the I/O bus as
shown in Figure 1.
Figure 1. Status Bit Assignment
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
3859 FHD F11
DATA
Polling (I/O
7
)
The X28HC256 features
DATA
Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed.
DATA
Polling allows a simple
bit test operation to determine the status of the
X28HC256, eliminating additional interrupt inputs or
external hardware. During the internal programming
cycle, any attempt to read the last byte written will
produce the complement of that data on I/O
7
(i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
programming cycle is complete, I/O
7
will reflect true
data.
Toggle Bit (I/O
6
)
The X28HC256 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O
6
will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read and write operations.
3
X28HC256
DATA
POLLING I/O
7
Figure 2.
DATA
Polling Bus Sequence
LAST
WRITE
WE
CE
OE
VIH
I/O7
HIGH Z
VOL
An
An
An
An
An
An
An
3859 FHD F12
VOH
X28HC256
READY
A0–A14
Figure 3.
DATA
Polling Software Flow
DATA
Polling can effectively halve the time for writing to
the X28HC256. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
WRITE DATA
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
NO
READ LAST
ADDRESS
IO7
COMPARE?
YES
X28HC256
READY
NO
3859 FHD F13
4
X28HC256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
VOH
*
VOL
I/O6
HIGH Z
*
X28HC256
READY
* I/O6 beginning and ending state of I/O6 will vary.
3859 FHD F14
Figure 5. Toggle Bit Software Flow
The Toggle Bit can eliminate the software housekeeping
chore of saving and fetching the last address and data
written to a device in order to implement
DATA
Polling.
This can be especially helpful in an array comprised of
multiple X28HC256 memories that is frequently up-
dated. The timing diagram in Figure 4 illustrates the
sequence of events on the bus. The software flow
diagram in Figure 5 illustrates a method for polling the
Toggle Bit.
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
COMPARE
OK?
YES
X28HC256
READY
NO
3859 FHD F15
5
